Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	16491367	40814	0	0
RomAllowCheckGoodState_A	16491367	40864	0	0
RomBlockActiveState_A	16491367	33103	0	0
RomBlockCheckGoodState_A	16491367	376494	0	0
RomIntgChkDisFalse_A	16491367	15989265	0	0
RomIntgChkDisTrue_A	16491367	119140	0	0
RstreqChkEsctimeout_A	16491367	2885	0	0
RstreqChkFsmterm_A	16491367	160	0	0
RstreqChkGlbesc_A	16491367	2888	0	0
RstreqChkMainpd_A	16491367	726530	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	40814	0	0
T1	5807	9	0	0
T2	3150	4	0	0
T3	4800	8	0	0
T4	3209	5	0	0
T5	1011	3	0	0
T6	4263	4	0	0
T7	8609	13	0	0
T8	7707	13	0	0
T9	3229	3	0	0
T10	3216	13	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	40864	0	0
T1	5807	9	0	0
T2	3150	4	0	0
T3	4800	8	0	0
T4	3209	5	0	0
T5	1011	3	0	0
T6	4263	4	0	0
T7	8609	14	0	0
T8	7707	14	0	0
T9	3229	3	0	0
T10	3216	14	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	33103	0	0
T1	5807	1266	0	0
T2	3150	0	0	0
T3	4800	796	0	0
T4	3209	0	0	0
T5	1011	0	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T15	0	10	0	0
T130	0	3	0	0
T131	0	228	0	0
T132	0	221	0	0
T133	0	1188	0	0
T134	0	6	0	0
T135	0	537	0	0
T136	0	49	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	376494	0	0
T1	5807	639	0	0
T2	3150	0	0	0
T3	4800	829	0	0
T4	3209	0	0	0
T5	1011	0	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T15	0	1269	0	0
T30	0	1920	0	0
T46	0	366	0	0
T47	0	1351	0	0
T77	0	299	0	0
T122	0	207	0	0
T137	0	2079	0	0
T138	0	229	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	15989265	0	0
T1	5807	3605	0	0
T2	3150	3063	0	0
T3	4800	3650	0	0
T4	3209	3112	0	0
T5	1011	931	0	0
T6	4263	4197	0	0
T7	8609	7709	0	0
T8	7707	6746	0	0
T9	3229	3179	0	0
T10	3216	2261	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	119140	0	0
T1	5807	2063	0	0
T2	3150	0	0	0
T3	4800	1100	0	0
T4	3209	0	0	0
T5	1011	0	0	0
T6	4263	0	0	0
T7	8609	0	0	0
T8	7707	0	0	0
T9	3229	0	0	0
T10	3216	0	0	0
T30	0	325	0	0
T117	0	2709	0	0
T130	0	281	0	0
T131	0	68	0	0
T132	0	179	0	0
T133	0	1590	0	0
T139	0	9574	0	0
T140	0	527	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	2885	0	0
T1	5807	1	0	0
T2	3150	0	0	0
T3	4800	2	0	0
T4	3209	0	0	0
T5	1011	0	0	0
T6	4263	0	0	0
T7	8609	8	0	0
T8	7707	6	0	0
T9	3229	0	0	0
T10	3216	5	0	0
T11	0	1	0	0
T14	0	1	0	0
T41	0	8	0	0
T42	0	5	0	0
T43	0	6	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	160	0	0
T22	40420	40	0	0
T23	17356	40	0	0
T24	0	20	0	0
T31	0	20	0	0
T32	0	40	0	0
T33	17055	0	0	0
T34	2748	0	0	0
T35	1676	0	0	0
T36	13575	0	0	0
T37	4840	0	0	0
T38	2102	0	0	0
T39	21406	0	0	0
T40	5014	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	2888	0	0
T1	5807	1	0	0
T2	3150	0	0	0
T3	4800	2	0	0
T4	3209	0	0	0
T5	1011	0	0	0
T6	4263	0	0	0
T7	8609	8	0	0
T8	7707	6	0	0
T9	3229	0	0	0
T10	3216	5	0	0
T11	0	1	0	0
T14	0	1	0	0
T41	0	8	0	0
T42	0	6	0	0
T43	0	6	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16491367	726530	0	0
T1	5807	1330	0	0
T2	3150	0	0	0
T3	4800	645	0	0
T4	3209	0	0	0
T5	1011	0	0	0
T6	4263	0	0	0
T7	8609	286	0	0
T8	7707	236	0	0
T9	3229	0	0	0
T10	3216	71	0	0
T14	0	21	0	0
T15	0	1379	0	0
T41	0	357	0	0
T42	0	56	0	0
T43	0	113	0	0