Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25582 1 T1 78 T2 16 T3 23
auto[1] 24539 1 T1 80 T2 10 T3 28


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25239 1 T1 88 T2 14 T3 30
auto[1] 24882 1 T1 70 T2 12 T3 21


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24501 1 T1 76 T2 20 T3 23
auto[1] 25620 1 T1 82 T2 6 T3 28


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28195 1 T1 79 T2 13 T3 41
auto[1] 21926 1 T1 79 T2 13 T3 10


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24657 1 T1 68 T2 14 T3 22
auto[1] 25464 1 T1 90 T2 12 T3 29


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25589 1 T1 92 T2 14 T3 28
auto[1] 24532 1 T1 66 T2 12 T3 23


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 830 1 T1 1 T2 1 T8 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 639 1 T1 1 T2 1 T24 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 884 1 T1 2 T2 1 T3 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 693 1 T1 2 T2 1 T7 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 913 1 T1 2 T3 1 T5 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 691 1 T1 2 T7 1 T24 5
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1378 1 T1 8 T3 1 T5 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1165 1 T1 8 T3 1 T5 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 888 1 T1 1 T2 1 T3 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 679 1 T1 1 T2 1 T7 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 805 1 T1 2 T3 3 T7 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 617 1 T1 2 T3 1 T7 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 856 1 T1 3 T3 1 T5 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 660 1 T1 3 T7 3 T24 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 815 1 T1 4 T3 1 T5 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 649 1 T1 4 T8 2 T24 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 856 1 T1 1 T8 2 T69 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 654 1 T1 1 T69 1 T24 4
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 909 1 T1 2 T3 2 T5 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 693 1 T1 2 T3 1 T7 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 834 1 T1 3 T2 2 T3 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 646 1 T1 3 T2 2 T8 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 836 1 T1 1 T3 3 T5 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 651 1 T1 1 T3 1 T5 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 882 1 T1 3 T5 2 T7 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 692 1 T1 3 T7 2 T41 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 891 1 T5 1 T7 2 T8 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 687 1 T7 2 T8 1 T24 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 881 1 T2 3 T3 1 T7 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 693 1 T2 3 T7 3 T8 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 896 1 T1 6 T5 3 T7 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 719 1 T1 6 T7 3 T10 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 871 1 T1 4 T2 1 T3 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 674 1 T1 4 T2 1 T7 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 882 1 T1 2 T2 2 T3 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 697 1 T1 2 T2 2 T3 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 837 1 T1 3 T3 2 T5 3
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 632 1 T1 3 T3 1 T7 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 872 1 T1 3 T5 2 T7 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 663 1 T1 3 T5 1 T7 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 846 1 T1 2 T2 1 T3 3
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 657 1 T1 2 T2 1 T7 4
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 858 1 T1 2 T3 1 T5 3
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 654 1 T1 2 T3 1 T8 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 799 1 T1 5 T3 2 T7 3
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 621 1 T1 5 T7 3 T24 3
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 857 1 T3 2 T7 1 T8 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 657 1 T3 1 T7 1 T24 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 860 1 T1 6 T5 1 T7 3
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 665 1 T1 6 T7 3 T8 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 863 1 T1 1 T3 1 T5 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 665 1 T1 1 T24 1 T111 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 875 1 T1 2 T3 2 T5 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 682 1 T1 2 T5 2 T7 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 886 1 T1 5 T3 1 T5 3
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 693 1 T1 5 T3 1 T5 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 918 1 T1 2 T3 1 T7 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 710 1 T1 2 T7 1 T24 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 866 1 T1 3 T5 1 T8 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 672 1 T1 3 T5 1 T41 4
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 889 1 T2 1 T3 2 T5 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 671 1 T2 1 T3 1 T7 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 862 1 T3 1 T5 2 T8 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 685 1 T5 1 T24 1 T41 2

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