Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3393 |
1 |
|
|
T3 |
3 |
|
T5 |
3 |
|
T6 |
2 |
auto[1] |
12376 |
1 |
|
|
T1 |
50 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7155 |
1 |
|
|
T1 |
19 |
|
T2 |
1 |
|
T3 |
2 |
auto[1] |
8614 |
1 |
|
|
T1 |
31 |
|
T3 |
4 |
|
T5 |
4 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7759 |
1 |
|
|
T1 |
27 |
|
T2 |
1 |
|
T3 |
4 |
auto[1] |
8010 |
1 |
|
|
T1 |
23 |
|
T3 |
2 |
|
T5 |
4 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
808 |
1 |
|
|
T3 |
1 |
|
T45 |
1 |
|
T50 |
2 |
auto[0] |
auto[0] |
auto[1] |
732 |
1 |
|
|
T6 |
1 |
|
T15 |
8 |
|
T80 |
1 |
auto[0] |
auto[1] |
auto[0] |
2991 |
1 |
|
|
T1 |
10 |
|
T2 |
1 |
|
T3 |
1 |
auto[0] |
auto[1] |
auto[1] |
2624 |
1 |
|
|
T1 |
9 |
|
T26 |
7 |
|
T50 |
1 |
auto[1] |
auto[0] |
auto[0] |
836 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T45 |
1 |
auto[1] |
auto[0] |
auto[1] |
1017 |
1 |
|
|
T3 |
1 |
|
T5 |
3 |
|
T45 |
1 |
auto[1] |
auto[1] |
auto[0] |
3124 |
1 |
|
|
T1 |
17 |
|
T3 |
1 |
|
T26 |
9 |
auto[1] |
auto[1] |
auto[1] |
3637 |
1 |
|
|
T1 |
14 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3393 |
1 |
|
|
T3 |
3 |
|
T5 |
3 |
|
T6 |
2 |
auto[1] |
12376 |
1 |
|
|
T1 |
50 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7095 |
1 |
|
|
T1 |
30 |
|
T2 |
1 |
|
T3 |
3 |
auto[1] |
8674 |
1 |
|
|
T1 |
20 |
|
T3 |
3 |
|
T5 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7743 |
1 |
|
|
T1 |
24 |
|
T3 |
2 |
|
T5 |
3 |
auto[1] |
8026 |
1 |
|
|
T1 |
26 |
|
T2 |
1 |
|
T3 |
4 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
815 |
1 |
|
|
T15 |
11 |
|
T80 |
1 |
|
T22 |
14 |
auto[0] |
auto[0] |
auto[1] |
714 |
1 |
|
|
T3 |
1 |
|
T45 |
2 |
|
T50 |
2 |
auto[0] |
auto[1] |
auto[0] |
2979 |
1 |
|
|
T1 |
17 |
|
T3 |
1 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
2587 |
1 |
|
|
T1 |
13 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[0] |
auto[0] |
853 |
1 |
|
|
T5 |
2 |
|
T6 |
1 |
|
T45 |
1 |
auto[1] |
auto[0] |
auto[1] |
1011 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[0] |
3096 |
1 |
|
|
T1 |
7 |
|
T3 |
1 |
|
T26 |
16 |
auto[1] |
auto[1] |
auto[1] |
3714 |
1 |
|
|
T1 |
13 |
|
T26 |
11 |
|
T50 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3393 |
1 |
|
|
T3 |
3 |
|
T5 |
3 |
|
T6 |
2 |
auto[1] |
12376 |
1 |
|
|
T1 |
50 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7142 |
1 |
|
|
T1 |
21 |
|
T3 |
3 |
|
T5 |
3 |
auto[1] |
8627 |
1 |
|
|
T1 |
29 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7792 |
1 |
|
|
T1 |
25 |
|
T3 |
3 |
|
T5 |
4 |
auto[1] |
7977 |
1 |
|
|
T1 |
25 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
837 |
1 |
|
|
T5 |
3 |
|
T50 |
1 |
|
T66 |
1 |
auto[0] |
auto[0] |
auto[1] |
731 |
1 |
|
|
T45 |
1 |
|
T50 |
1 |
|
T66 |
1 |
auto[0] |
auto[1] |
auto[0] |
2994 |
1 |
|
|
T1 |
13 |
|
T3 |
2 |
|
T6 |
1 |
auto[0] |
auto[1] |
auto[1] |
2580 |
1 |
|
|
T1 |
8 |
|
T3 |
1 |
|
T26 |
10 |
auto[1] |
auto[0] |
auto[0] |
840 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T45 |
1 |
auto[1] |
auto[0] |
auto[1] |
985 |
1 |
|
|
T3 |
2 |
|
T6 |
1 |
|
T45 |
1 |
auto[1] |
auto[1] |
auto[0] |
3121 |
1 |
|
|
T1 |
12 |
|
T5 |
1 |
|
T26 |
9 |
auto[1] |
auto[1] |
auto[1] |
3681 |
1 |
|
|
T1 |
17 |
|
T2 |
1 |
|
T26 |
17 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3393 |
1 |
|
|
T3 |
3 |
|
T5 |
3 |
|
T6 |
2 |
auto[1] |
12376 |
1 |
|
|
T1 |
50 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7123 |
1 |
|
|
T1 |
22 |
|
T3 |
4 |
|
T5 |
1 |
auto[1] |
8646 |
1 |
|
|
T1 |
28 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7748 |
1 |
|
|
T1 |
32 |
|
T3 |
4 |
|
T5 |
1 |
auto[1] |
8021 |
1 |
|
|
T1 |
18 |
|
T2 |
1 |
|
T3 |
2 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
863 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T6 |
1 |
auto[0] |
auto[0] |
auto[1] |
740 |
1 |
|
|
T6 |
1 |
|
T50 |
1 |
|
T66 |
1 |
auto[0] |
auto[1] |
auto[0] |
2950 |
1 |
|
|
T1 |
15 |
|
T3 |
1 |
|
T26 |
10 |
auto[0] |
auto[1] |
auto[1] |
2570 |
1 |
|
|
T1 |
7 |
|
T3 |
1 |
|
T44 |
1 |
auto[1] |
auto[0] |
auto[0] |
834 |
1 |
|
|
T15 |
12 |
|
T80 |
3 |
|
T22 |
10 |
auto[1] |
auto[0] |
auto[1] |
956 |
1 |
|
|
T3 |
1 |
|
T5 |
2 |
|
T45 |
2 |
auto[1] |
auto[1] |
auto[0] |
3101 |
1 |
|
|
T1 |
17 |
|
T3 |
1 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[1] |
3755 |
1 |
|
|
T1 |
11 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3393 |
1 |
|
|
T3 |
3 |
|
T5 |
3 |
|
T6 |
2 |
auto[1] |
12376 |
1 |
|
|
T1 |
50 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7054 |
1 |
|
|
T1 |
20 |
|
T3 |
1 |
|
T5 |
3 |
auto[1] |
8715 |
1 |
|
|
T1 |
30 |
|
T2 |
1 |
|
T3 |
5 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7794 |
1 |
|
|
T1 |
23 |
|
T3 |
3 |
|
T5 |
1 |
auto[1] |
7975 |
1 |
|
|
T1 |
27 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
846 |
1 |
|
|
T66 |
1 |
|
T60 |
1 |
|
T15 |
8 |
auto[0] |
auto[0] |
auto[1] |
693 |
1 |
|
|
T5 |
2 |
|
T45 |
1 |
|
T15 |
9 |
auto[0] |
auto[1] |
auto[0] |
2979 |
1 |
|
|
T1 |
8 |
|
T5 |
1 |
|
T26 |
10 |
auto[0] |
auto[1] |
auto[1] |
2536 |
1 |
|
|
T1 |
12 |
|
T3 |
1 |
|
T6 |
1 |
auto[1] |
auto[0] |
auto[0] |
854 |
1 |
|
|
T3 |
2 |
|
T6 |
1 |
|
T45 |
2 |
auto[1] |
auto[0] |
auto[1] |
1000 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[0] |
3115 |
1 |
|
|
T1 |
15 |
|
T3 |
1 |
|
T26 |
12 |
auto[1] |
auto[1] |
auto[1] |
3746 |
1 |
|
|
T1 |
15 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3393 |
1 |
|
|
T3 |
3 |
|
T5 |
3 |
|
T6 |
2 |
auto[1] |
12376 |
1 |
|
|
T1 |
50 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7078 |
1 |
|
|
T1 |
25 |
|
T3 |
3 |
|
T5 |
2 |
auto[1] |
8691 |
1 |
|
|
T1 |
25 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7819 |
1 |
|
|
T1 |
24 |
|
T2 |
1 |
|
T3 |
4 |
auto[1] |
7950 |
1 |
|
|
T1 |
26 |
|
T3 |
2 |
|
T5 |
1 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
833 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T6 |
1 |
auto[0] |
auto[0] |
auto[1] |
755 |
1 |
|
|
T45 |
1 |
|
T66 |
2 |
|
T15 |
5 |
auto[0] |
auto[1] |
auto[0] |
2990 |
1 |
|
|
T1 |
13 |
|
T3 |
1 |
|
T5 |
1 |
auto[0] |
auto[1] |
auto[1] |
2500 |
1 |
|
|
T1 |
12 |
|
T3 |
1 |
|
T26 |
15 |
auto[1] |
auto[0] |
auto[0] |
830 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T50 |
1 |
auto[1] |
auto[0] |
auto[1] |
975 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T15 |
12 |
auto[1] |
auto[1] |
auto[0] |
3166 |
1 |
|
|
T1 |
11 |
|
T2 |
1 |
|
T26 |
12 |
auto[1] |
auto[1] |
auto[1] |
3720 |
1 |
|
|
T1 |
14 |
|
T3 |
1 |
|
T6 |
1 |