Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	365463	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

186948

1

T1

241

T2

14

T3

84

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	354112	1			T1	521		T2	19		T3	125
values[0x0]	98910	1			T1	201		T2	10		T3	30
values[0x1]	99389	1			T1	251		T2	6		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	289503	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

262908

1

T1

397

T2

15

T3

102

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2608	1			T5	1		T44	2		T26	7
valid_sources[0x01]	1898	1			T14	2		T26	3		T66	1
valid_sources[0x02]	1706	1			T3	1		T5	1		T26	5
valid_sources[0x03]	2006	1			T26	9		T27	1		T28	6
valid_sources[0x04]	1798	1			T5	1		T14	1		T28	7
valid_sources[0x05]	1744	1			T5	1		T26	4		T66	1
valid_sources[0x06]	3043	1			T13	2		T26	3		T27	1
valid_sources[0x07]	1950	1			T3	2		T5	1		T26	3
valid_sources[0x08]	1797	1			T3	2		T26	5		T28	7
valid_sources[0x09]	2108	1			T14	2		T26	7		T28	3
valid_sources[0x0a]	2939	1			T3	1		T26	3		T28	7
valid_sources[0x0b]	1903	1			T3	2		T26	8		T28	3
valid_sources[0x0c]	1887	1			T5	1		T44	2		T14	3
valid_sources[0x0d]	1745	1			T26	6		T66	2		T28	5
valid_sources[0x0e]	2962	1			T5	3		T44	1		T14	1
valid_sources[0x0f]	1811	1			T26	4		T27	1		T28	4
valid_sources[0x10]	1890	1			T13	1		T26	8		T28	4
valid_sources[0x11]	1767	1			T26	2		T28	4		T15	2
valid_sources[0x12]	2037	1			T5	2		T13	2		T14	5
valid_sources[0x13]	1666	1			T3	1		T6	4		T13	3
valid_sources[0x14]	1709	1			T13	1		T26	2		T66	1
valid_sources[0x15]	2065	1			T45	59		T26	5		T66	2
valid_sources[0x16]	2599	1			T5	2		T10	1		T26	10
valid_sources[0x17]	1780	1			T13	1		T26	6		T28	4
valid_sources[0x18]	1968	1			T26	15		T28	7		T15	3
valid_sources[0x19]	2026	1			T14	6		T26	4		T66	1
valid_sources[0x1a]	1810	1			T3	4		T5	1		T14	2
valid_sources[0x1b]	1876	1			T5	1		T13	1		T26	7
valid_sources[0x1c]	1899	1			T26	4		T27	1		T28	2
valid_sources[0x1d]	1810	1			T3	1		T5	3		T26	9
valid_sources[0x1e]	1666	1			T3	3		T13	1		T26	5
valid_sources[0x1f]	1740	1			T3	8		T14	1		T26	2
valid_sources[0x20]	1765	1			T26	8		T27	1		T28	5
valid_sources[0x21]	1881	1			T3	2		T26	4		T66	3
valid_sources[0x22]	11145	1			T26	3		T28	2		T15	9
valid_sources[0x23]	1745	1			T5	1		T14	3		T26	7
valid_sources[0x24]	1607	1			T26	5		T28	5		T15	8
valid_sources[0x25]	1944	1			T3	1		T13	1		T26	4
valid_sources[0x26]	1657	1			T3	1		T13	4		T26	10
valid_sources[0x27]	2007	1			T26	7		T28	2		T80	4
valid_sources[0x28]	1750	1			T26	6		T28	3		T15	16
valid_sources[0x29]	1863	1			T5	3		T26	6		T66	6
valid_sources[0x2a]	1908	1			T44	2		T13	1		T14	4
valid_sources[0x2b]	1701	1			T3	6		T5	1		T26	6
valid_sources[0x2c]	1692	1			T14	1		T26	5		T27	1
valid_sources[0x2d]	1898	1			T2	6		T5	1		T13	1
valid_sources[0x2e]	1632	1			T13	2		T26	8		T28	8
valid_sources[0x2f]	3706	1			T26	4		T66	1		T28	4
valid_sources[0x30]	1760	1			T26	5		T28	6		T15	4
valid_sources[0x31]	1805	1			T13	1		T26	13		T27	1
valid_sources[0x32]	3590	1			T3	1		T5	1		T14	3
valid_sources[0x33]	1879	1			T5	2		T6	1		T13	1
valid_sources[0x34]	2015	1			T3	2		T26	4		T27	3
valid_sources[0x35]	3238	1			T13	1		T14	1		T26	9
valid_sources[0x36]	2789	1			T3	1		T5	2		T13	3
valid_sources[0x37]	1679	1			T26	5		T66	4		T28	9
valid_sources[0x38]	1749	1			T3	2		T13	2		T26	1
valid_sources[0x39]	2011	1			T26	7		T50	3		T66	1
valid_sources[0x3a]	1594	1			T26	5		T12	1		T28	4
valid_sources[0x3b]	1876	1			T13	2		T26	10		T28	2
valid_sources[0x3c]	1810	1			T13	1		T26	5		T28	8
valid_sources[0x3d]	1884	1			T3	6		T5	1		T14	1
valid_sources[0x3e]	1968	1			T44	1		T26	8		T27	1
valid_sources[0x3f]	1806	1			T26	11		T28	10		T15	9
valid_sources[0x40]	1798	1			T3	1		T14	4		T26	7
valid_sources[0x41]	1789	1			T26	6		T27	1		T28	5
valid_sources[0x42]	1860	1			T26	10		T28	5		T15	20
valid_sources[0x43]	1817	1			T26	7		T28	2		T15	7
valid_sources[0x44]	1984	1			T3	1		T26	5		T50	1
valid_sources[0x45]	1877	1			T3	1		T5	1		T26	2
valid_sources[0x46]	1802	1			T13	1		T26	5		T50	2
valid_sources[0x47]	1825	1			T3	1		T5	1		T26	4
valid_sources[0x48]	1636	1			T3	1		T14	2		T26	15
valid_sources[0x49]	1811	1			T26	3		T28	4		T15	3
valid_sources[0x4a]	1927	1			T2	13		T3	11		T13	1
valid_sources[0x4b]	1800	1			T3	1		T13	2		T26	6
valid_sources[0x4c]	1610	1			T26	6		T66	4		T28	5
valid_sources[0x4d]	1792	1			T26	5		T50	4		T28	3
valid_sources[0x4e]	3127	1			T26	7		T28	4		T15	2
valid_sources[0x4f]	2062	1			T5	1		T26	6		T50	1
valid_sources[0x50]	2178	1			T3	1		T6	8		T13	1
valid_sources[0x51]	1783	1			T3	1		T26	2		T28	4
valid_sources[0x52]	1665	1			T2	1		T13	1		T14	1
valid_sources[0x53]	1734	1			T5	2		T26	5		T27	1
valid_sources[0x54]	1710	1			T3	3		T14	4		T26	6
valid_sources[0x55]	1751	1			T44	1		T14	3		T26	7
valid_sources[0x56]	1605	1			T3	6		T5	1		T26	8
valid_sources[0x57]	2371	1			T5	2		T13	1		T26	8
valid_sources[0x58]	2147	1			T44	1		T14	1		T26	7
valid_sources[0x59]	2661	1			T5	1		T6	8		T13	1
valid_sources[0x5a]	1919	1			T3	1		T26	5		T28	2
valid_sources[0x5b]	3040	1			T3	4		T26	2		T28	6
valid_sources[0x5c]	1826	1			T5	1		T44	1		T14	2
valid_sources[0x5d]	1626	1			T5	3		T26	7		T66	6
valid_sources[0x5e]	1789	1			T3	3		T5	1		T44	1
valid_sources[0x5f]	2857	1			T26	6		T50	1		T66	2
valid_sources[0x60]	3824	1			T5	1		T26	8		T66	3
valid_sources[0x61]	1734	1			T26	8		T28	9		T15	2
valid_sources[0x62]	1836	1			T3	1		T26	4		T50	2
valid_sources[0x63]	1733	1			T3	4		T14	4		T26	5
valid_sources[0x64]	2111	1			T44	1		T26	5		T28	7
valid_sources[0x65]	1946	1			T26	3		T28	6		T15	6
valid_sources[0x66]	1814	1			T3	1		T14	3		T26	6
valid_sources[0x67]	1762	1			T2	2		T26	3		T28	6
valid_sources[0x68]	1867	1			T26	10		T27	2		T28	11
valid_sources[0x69]	1952	1			T26	5		T28	3		T15	13
valid_sources[0x6a]	1759	1			T3	2		T44	1		T26	8
valid_sources[0x6b]	1721	1			T26	5		T28	1		T15	4
valid_sources[0x6c]	1586	1			T13	2		T26	7		T28	4
valid_sources[0x6d]	1937	1			T13	2		T26	7		T28	5
valid_sources[0x6e]	1818	1			T26	5		T50	2		T28	7
valid_sources[0x6f]	1705	1			T13	2		T26	8		T27	2
valid_sources[0x70]	3002	1			T3	4		T26	9		T27	1
valid_sources[0x71]	1899	1			T13	3		T14	3		T26	7
valid_sources[0x72]	2104	1			T3	1		T26	9		T28	7
valid_sources[0x73]	1834	1			T13	1		T26	7		T28	11
valid_sources[0x74]	2774	1			T26	6		T28	2		T15	6
valid_sources[0x75]	1897	1			T13	1		T26	6		T28	9
valid_sources[0x76]	1941	1			T26	9		T28	6		T15	32
valid_sources[0x77]	1671	1			T3	1		T26	4		T28	5
valid_sources[0x78]	1814	1			T26	3		T28	10		T15	5
valid_sources[0x79]	2297	1			T2	1		T26	13		T28	3
valid_sources[0x7a]	1809	1			T26	8		T28	3		T15	1
valid_sources[0x7b]	1748	1			T5	2		T7	1		T26	4
valid_sources[0x7c]	1630	1			T26	6		T66	2		T28	4
valid_sources[0x7d]	2203	1			T26	6		T28	4		T15	2
valid_sources[0x7e]	1817	1			T3	2		T5	1		T14	1
valid_sources[0x7f]	1946	1			T5	2		T14	1		T26	2
valid_sources[0x80]	2003	1			T5	1		T26	9		T28	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

126918

1

T1

138

T2

11

T3

66

values[0x0]

all_enables

biggest_size

38043

1

T1

66

T2

2

T3

12

values[0x1]

all_enables

biggest_size

21987

1

T1

37

T2

1

T3

6