SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 33702 | 1 | T1 | 406 | T26 | 295 | T28 | 304 | ||||
others[1] | 33777 | 1 | T1 | 384 | T26 | 295 | T27 | 1 | ||||
others[2] | 34034 | 1 | T1 | 384 | T26 | 304 | T28 | 297 | ||||
others[3] | 56626 | 1 | T1 | 697 | T26 | 490 | T28 | 518 | ||||
false | 12332 | 1 | T1 | 50 | T26 | 50 | T27 | 3 | ||||
true | 19621 | 1 | T1 | 101 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34029 | 1 | T1 | 394 | T26 | 286 | T28 | 307 | ||||
others[1] | 33880 | 1 | T1 | 407 | T26 | 300 | T28 | 285 | ||||
others[2] | 33816 | 1 | T1 | 413 | T26 | 291 | T28 | 287 | ||||
others[3] | 56595 | 1 | T1 | 664 | T26 | 510 | T27 | 1 | ||||
false | 8677 | 1 | T1 | 50 | T26 | 50 | T27 | 2 | ||||
true | 16014 | 1 | T1 | 101 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 462 | 1 | T4 | 4 | T14 | 2 | T15 | 2 | ||||
others[1] | 475 | 1 | T4 | 8 | T13 | 1 | T27 | 1 | ||||
others[2] | 453 | 1 | T4 | 5 | T14 | 2 | T15 | 2 | ||||
others[3] | 768 | 1 | T4 | 7 | T14 | 2 | T27 | 1 | ||||
false | 8232 | 1 | T1 | 1 | T2 | 5 | T3 | 1 | ||||
true | 2190 | 1 | T4 | 2 | T13 | 7 | T14 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |