Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T28,T22

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	14649958	4157	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	14649958	170043	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	14649958	5762569	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	14649958	170064	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	14649958	4157	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	14649958	170043	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	14649958	5762569	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	14649958	170064	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	4157	0	0
T1	21141	23	0	0
T2	3321	3	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T15	0	6	0	0
T22	0	25	0	0
T23	0	37	0	0
T26	0	24	0	0
T28	0	19	0	0
T40	0	4	0	0
T53	0	2	0	0
T79	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	170043	0	0
T1	21141	507	0	0
T2	3321	766	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T15	0	66	0	0
T22	0	757	0	0
T23	0	727	0	0
T26	0	661	0	0
T28	0	513	0	0
T40	0	220	0	0
T53	0	219	0	0
T79	0	14	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	5762569	0	0
T1	21141	11656	0	0
T2	3321	451	0	0
T3	4005	1594	0	0
T4	4869	0	0	0
T5	5466	2640	0	0
T6	2693	1070	0	0
T7	3281	0	0	0
T8	748	570	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T26	0	17422	0	0
T45	0	2189	0	0
T50	0	2446	0	0
T66	0	2792	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	170064	0	0
T1	21141	507	0	0
T2	3321	766	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T15	0	66	0	0
T22	0	757	0	0
T23	0	727	0	0
T26	0	661	0	0
T28	0	513	0	0
T40	0	220	0	0
T53	0	219	0	0
T79	0	14	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	4157	0	0
T1	21141	23	0	0
T2	3321	3	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T15	0	6	0	0
T22	0	25	0	0
T23	0	37	0	0
T26	0	24	0	0
T28	0	19	0	0
T40	0	4	0	0
T53	0	2	0	0
T79	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	170043	0	0
T1	21141	507	0	0
T2	3321	766	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T15	0	66	0	0
T22	0	757	0	0
T23	0	727	0	0
T26	0	661	0	0
T28	0	513	0	0
T40	0	220	0	0
T53	0	219	0	0
T79	0	14	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	5762569	0	0
T1	21141	11656	0	0
T2	3321	451	0	0
T3	4005	1594	0	0
T4	4869	0	0	0
T5	5466	2640	0	0
T6	2693	1070	0	0
T7	3281	0	0	0
T8	748	570	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T26	0	17422	0	0
T45	0	2189	0	0
T50	0	2446	0	0
T66	0	2792	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	170064	0	0
T1	21141	507	0	0
T2	3321	766	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T15	0	66	0	0
T22	0	757	0	0
T23	0	727	0	0
T26	0	661	0	0
T28	0	513	0	0
T40	0	220	0	0
T53	0	219	0	0
T79	0	14	0	0