Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	15234522	13305	0	0
intr_enable_rd_A	15234522	14849	0	0
reset_en_rd_A	15234522	1087	0	0
reset_en_regwen_rd_A	15234522	974	0	0
wake_info_capture_dis_rd_A	15234522	919	0	0
wakeup_en_rd_A	15234522	1537	0	0
wakeup_en_regwen_rd_A	15234522	986	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	13305	0	0
T22	68321	6	0	0
T23	114493	10	0	0
T24	218431	5	0	0
T25	1741	0	0	0
T43	1819	0	0	0
T48	1918	0	0	0
T49	2336	0	0	0
T54	0	527	0	0
T55	0	464	0	0
T56	0	579	0	0
T57	0	13	0	0
T74	0	106	0	0
T81	0	2	0	0
T82	0	59	0	0
T125	2978	0	0	0
T126	1865	0	0	0
T127	2295	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	14849	0	0
T4	4869	64	0	0
T5	5466	10	0	0
T6	2693	9	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T13	2772	0	0	0
T14	0	60	0	0
T24	0	1551	0	0
T27	0	15	0	0
T44	3225	0	0	0
T45	4471	0	0	0
T50	0	16	0	0
T79	0	4	0	0
T127	0	30	0	0
T128	0	151	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	1087	0	0
T57	11299	57	0	0
T65	2201	0	0	0
T78	0	16	0	0
T81	981	0	0	0
T82	4751	11	0	0
T83	700	0	0	0
T84	1509	0	0	0
T88	1895	12	0	0
T89	1217	1	0	0
T90	0	28	0	0
T95	0	43	0	0
T123	1267	3	0	0
T124	1231	0	0	0
T129	0	2	0	0
T130	0	64	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	974	0	0
T57	11299	39	0	0
T65	2201	0	0	0
T76	0	7	0	0
T78	0	24	0	0
T81	981	0	0	0
T82	4751	3	0	0
T83	700	0	0	0
T84	1509	0	0	0
T88	1895	3	0	0
T89	1217	3	0	0
T90	0	80	0	0
T95	0	24	0	0
T123	1267	8	0	0
T124	1231	0	0	0
T130	0	43	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	919	0	0
T24	218431	1	0	0
T57	0	32	0	0
T82	0	5	0	0
T88	0	5	0	0
T89	0	8	0	0
T90	0	27	0	0
T95	0	22	0	0
T123	0	4	0	0
T126	1865	0	0	0
T127	2295	0	0	0
T129	0	12	0	0
T130	0	62	0	0
T131	1364	0	0	0
T132	5360	0	0	0
T133	1609	0	0	0
T134	2986	0	0	0
T135	15306	0	0	0
T136	1679	0	0	0
T137	14864	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	1537	0	0
T57	11299	171	0	0
T58	6300	0	0	0
T76	0	4	0	0
T78	0	12	0	0
T82	4751	6	0	0
T83	700	0	0	0
T84	1509	0	0	0
T86	1024	0	0	0
T87	1092	0	0	0
T88	1895	20	0	0
T89	1217	1	0	0
T90	2563	31	0	0
T95	0	68	0	0
T129	0	9	0	0
T130	0	70	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	986	0	0
T57	11299	50	0	0
T65	2201	0	0	0
T76	0	6	0	0
T81	981	0	0	0
T82	4751	15	0	0
T83	700	0	0	0
T84	1509	0	0	0
T86	1024	0	0	0
T88	1895	1	0	0
T90	0	37	0	0
T95	0	50	0	0
T98	0	10	0	0
T123	1267	2	0	0
T124	1231	0	0	0
T129	0	6	0	0
T130	0	82	0	0