Unified Coverage Report :: Module :: pwrmgr_reg_top

Module : pwrmgr_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.24	96.01	97.64	100.00		92.53	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_cdc_sync	100.00	100.00	100.00			100.00
u_cfg_cdc_sync0_qe	100.00	100.00				100.00
u_chk	100.00	100.00		100.00			100.00
u_control_core_clk_en	100.00	100.00	100.00			100.00
u_control_io_clk_en	100.00	100.00	100.00			100.00
u_control_low_power_hint	100.00	100.00	100.00			100.00
u_control_main_pd_n	100.00	100.00	100.00			100.00
u_control_usb_clk_en_active	100.00	100.00	100.00			100.00
u_control_usb_clk_en_lp	100.00	100.00	100.00			100.00
u_ctrl_cfg_regwen	100.00	100.00
u_escalate_reset_status	62.59	77.78	50.00			60.00
u_fault_status_esc_timeout	96.30	88.89	100.00			100.00
u_fault_status_main_pd_glitch	100.00	100.00	100.00			100.00
u_fault_status_reg_intg_err	96.30	88.89	100.00			100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_reset_en_en_0	100.00	100.00	100.00			100.00
u_reset_en_en_1	100.00	100.00	100.00			100.00
u_reset_en_regwen	100.00	100.00	100.00			100.00
u_reset_status_val_0	62.59	77.78	50.00			60.00
u_reset_status_val_1	62.59	77.78	50.00			60.00
u_rsp_intg_gen	100.00	100.00					100.00
u_wake_info_abort	100.00	100.00
u_wake_info_capture_dis	100.00	100.00	100.00			100.00
u_wake_info_fall_through	100.00	100.00
u_wake_info_reasons	100.00	100.00
u_wake_status_val_0	62.59	77.78	50.00			60.00
u_wake_status_val_1	62.59	77.78	50.00			60.00
u_wake_status_val_2	62.59	77.78	50.00			60.00
u_wake_status_val_3	62.59	77.78	50.00			60.00
u_wake_status_val_4	62.59	77.78	50.00			60.00
u_wake_status_val_5	62.59	77.78	50.00			60.00
u_wakeup_en_en_0	100.00	100.00	100.00			100.00
u_wakeup_en_en_1	100.00	100.00	100.00			100.00
u_wakeup_en_en_2	100.00	100.00	100.00			100.00
u_wakeup_en_en_3	100.00	100.00	100.00			100.00
u_wakeup_en_en_4	100.00	100.00	100.00			100.00
u_wakeup_en_en_5	100.00	100.00	100.00			100.00
u_wakeup_en_regwen	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_reg_top

	Line No.	Total	Covered	Percent
TOTAL		140	140	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	1092	1	1	100.00
CONT_ASSIGN	1107	1	1	100.00
CONT_ASSIGN	1123	1	1	100.00
CONT_ASSIGN	1139	1	1	100.00
ALWAYS	1231	18	18	100.00
CONT_ASSIGN	1251	1	1	100.00
ALWAYS	1255	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1308	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1314	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1321	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1333	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
ALWAYS	1343	18	18	100.00
ALWAYS	1365	40	40	100.00
CONT_ASSIGN	1467	0	0
CONT_ASSIGN	1475	1	1	100.00
CONT_ASSIGN	1476	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv' or '../src/lowrisc_ip_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
94	1	1
95	1	1
123	1	1
124	1	1
267	1	1
281	1	1
287	1	1
301	1	1
323	1	1
524	1	1
559	1	1
920	1	1
1092	1	1
1107	1	1
1123	1	1
1139	1	1
1231	1	1
1232	1	1
1233	1	1
1234	1	1
1235	1	1
1236	1	1
1237	1	1
1238	1	1
1239	1	1
1240	1	1
1241	1	1
1242	1	1
1243	1	1
1244	1	1
1245	1	1
1246	1	1
1247	1	1
1248	1	1
1251	1	1
1255	1	1
1276	1	1
1278	1	1
1279	1	1
1281	1	1
1282	1	1
1284	1	1
1285	1	1
1287	1	1
1288	1	1
1289	1	1
1291	1	1
1293	1	1
1295	1	1
1297	1	1
1299	1	1
1301	1	1
1302	1	1
1304	1	1
1305	1	1
1307	1	1
1308	1	1
1310	1	1
1312	1	1
1314	1	1
1316	1	1
1318	1	1
1320	1	1
1321	1	1
1323	1	1
1324	1	1
1326	1	1
1328	1	1
1329	1	1
1331	1	1
1332	1	1
1333	1	1
1335	1	1
1337	1	1
1339	1	1
1343	1	1
1344	1	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1359	1	1
1360	1	1
1365	1	1
1366	1	1
1368	1	1
1372	1	1
1376	1	1
1380	1	1
1384	1	1
1388	1	1
1389	1	1
1390	1	1
1391	1	1
1392	1	1
1393	1	1
1397	1	1
1401	1	1
1405	1	1
1406	1	1
1407	1	1
1408	1	1
1409	1	1
1410	1	1
1414	1	1
1415	1	1
1416	1	1
1417	1	1
1418	1	1
1419	1	1
1423	1	1
1427	1	1
1428	1	1
1432	1	1
1433	1	1
1437	1	1
1441	1	1
1445	1	1
1446	1	1
1447	1	1
1451	1	1
1452	1	1
1453	1	1
1467		unreachable
1475	1	1
1476	1	1

---

Cond Coverage for Module : pwrmgr_reg_top

	Total	Covered	Percent
Conditions	192	192	100.00
Logical	192	192	100.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T54,T55,T56
1	1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T20,T21
1	0	Covered	T57,T58,T59

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T19,T20,T21
0	1	0	Covered	T57,T58,T59
1	0	0	Covered	T57,T58,T59

 LINE       124
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T57,T58,T59
0	1	0	Covered	T54,T55,T56
1	0	0	Covered	T54,T55,T56

 LINE       124
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T54,T55,T56

 LINE       323
 EXPRESSION (control_we & ctrl_cfg_regwen_qs)
             -----1----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T60
1	1	Covered	T1,T2,T3

 LINE       559
 EXPRESSION (wakeup_en_we & wakeup_en_regwen_qs)
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T61,T62,T63
1	1	Covered	T1,T2,T3

 LINE       920
 EXPRESSION (reset_en_we & reset_en_regwen_qs)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T61,T64,T65
1	1	Covered	T1,T13,T14

 LINE       1232
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1233
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1234
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       1235
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T13

 LINE       1236
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       1237
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1238
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1239
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       1240
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1241
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1242
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       1243
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T8

 LINE       1244
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       1245
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       1246
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1247
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       1248
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_FAULT_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       1251
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1251
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1255
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T54,T55,T56

 LINE       1255
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T1,T4,T6
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T1,T4,T13
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T1,T4,T6
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T1,T4,T6
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T1,T4,T13
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T1,T4,T8
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T1,T4,T8
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T1,T4,T6
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T1,T4,T6
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T3,T4
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T4,T6
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T4,T66
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T6,T44
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T4,T13
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T4,T5

 LINE       1255
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       1255
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T13

 LINE       1255
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T44
1	1	Covered	T1,T6,T44

 LINE       1255
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T66

 LINE       1255
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T6

 LINE       1255
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1255
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1255
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T6

 LINE       1255
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       1255
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       1255
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T8

 LINE       1255
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T44
1	1	Covered	T1,T4,T8

 LINE       1255
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T13

 LINE       1255
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T6

 LINE       1255
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T6

 LINE       1255
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T13

 LINE       1255
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T6

 LINE       1276
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T55,T67
1	1	1	Covered	T1,T3,T4

 LINE       1279
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T55,T56
1	1	1	Covered	T1,T2,T3

 LINE       1282
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T54,T55,T56
1	1	1	Covered	T68,T69,T70

 LINE       1285
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T13
1	1	0	Covered	T54,T55,T56
1	1	1	Covered	T61,T62,T63

 LINE       1288
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T71,T72,T73
1	1	1	Covered	T22,T23,T74

 LINE       1289
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T56,T75
1	1	1	Covered	T1,T2,T3

 LINE       1302
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T55,T56
1	1	1	Covered	T1,T2,T3

 LINE       1305
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T54,T76,T77
1	1	1	Covered	T61,T62,T63

 LINE       1308
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T54,T55,T56
1	1	1	Covered	T1,T2,T3

 LINE       1321
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T54,T55,T56
1	1	1	Covered	T61,T62,T63

 LINE       1324
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T8
1	1	0	Covered	T54,T56,T78
1	1	1	Covered	T1,T13,T14

 LINE       1329
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T54,T56,T58
1	1	1	Covered	T1,T3,T4

 LINE       1332
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T58
1	1	1	Covered	T1,T3,T4

 LINE       1333
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T54,T55,T56
1	1	1	Covered	T1,T3,T4

---

Branch Coverage for Module : pwrmgr_reg_top

	Line No.	Total	Covered	Percent
Branches		23	23	100.00
TERNARY	1251	2	2	100.00
IF	73	3	3	100.00
CASE	1366	18	18	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv' or '../src/lowrisc_ip_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1251	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_lc_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T57,T58,T59
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1366	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	15234522	541712	0	0
reAfterRv	15234522	541680	0	0
rePulse	15234522	351442	0	0
wePulse	15234522	190238	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	541712	0	0
T1	21141	973	0	0
T2	3321	37	0	0
T3	4005	186	0	0
T4	4869	244	0	0
T5	5466	86	0	0
T6	2693	53	0	0
T7	3281	1	0	0
T8	748	11	0	0
T9	2013	1	0	0
T10	14910	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	541680	0	0
T1	21141	973	0	0
T2	3321	35	0	0
T3	4005	186	0	0
T4	4869	244	0	0
T5	5466	86	0	0
T6	2693	53	0	0
T7	3281	1	0	0
T8	748	11	0	0
T9	2013	1	0	0
T10	14910	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	351442	0	0
T1	21141	521	0	0
T2	3321	19	0	0
T3	4005	125	0	0
T4	4869	182	0	0
T5	5466	47	0	0
T6	2693	31	0	0
T7	3281	1	0	0
T8	748	4	0	0
T9	2013	1	0	0
T10	14910	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	15234522	190238	0	0
T1	21141	452	0	0
T2	3321	16	0	0
T3	4005	61	0	0
T4	4869	62	0	0
T5	5466	39	0	0
T6	2693	22	0	0
T7	3281	0	0	0
T8	748	7	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T13	0	33	0	0
T44	0	16	0	0
T45	0	22	0	0