Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	14649958	31403	0	0
IoStatusRise_A	14649958	34889	0	0
MainStatusFall_A	14649958	31404	0	0
MainStatusRise_A	14649958	34889	0	0
UsbStatusFall_A	14649958	23574	0	0
UsbStatusRise_A	14649958	26470	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	31403	0	0
T1	21141	84	0	0
T2	3321	4	0	0
T3	4005	6	0	0
T4	4869	2	0	0
T5	5466	4	0	0
T6	2693	3	0	0
T7	3281	0	0	0
T8	748	1	0	0
T9	2013	0	0	0
T10	14910	1	0	0
T13	0	18	0	0
T44	0	4	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	34889	0	0
T1	21141	85	0	0
T2	3321	5	0	0
T3	4005	7	0	0
T4	4869	3	0	0
T5	5466	5	0	0
T6	2693	4	0	0
T7	3281	5	0	0
T8	748	2	0	0
T9	2013	2	0	0
T10	14910	2	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	31404	0	0
T1	21141	84	0	0
T2	3321	4	0	0
T3	4005	6	0	0
T4	4869	2	0	0
T5	5466	4	0	0
T6	2693	3	0	0
T7	3281	0	0	0
T8	748	1	0	0
T9	2013	0	0	0
T10	14910	1	0	0
T13	0	18	0	0
T44	0	4	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	34889	0	0
T1	21141	85	0	0
T2	3321	5	0	0
T3	4005	7	0	0
T4	4869	3	0	0
T5	5466	5	0	0
T6	2693	4	0	0
T7	3281	5	0	0
T8	748	2	0	0
T9	2013	2	0	0
T10	14910	2	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	23574	0	0
T1	21141	46	0	0
T2	3321	4	0	0
T3	4005	4	0	0
T4	4869	2	0	0
T5	5466	2	0	0
T6	2693	3	0	0
T7	3281	0	0	0
T8	748	1	0	0
T9	2013	0	0	0
T10	14910	1	0	0
T13	0	18	0	0
T44	0	4	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	26470	0	0
T1	21141	47	0	0
T2	3321	5	0	0
T3	4005	5	0	0
T4	4869	3	0	0
T5	5466	2	0	0
T6	2693	3	0	0
T7	3281	5	0	0
T8	748	2	0	0
T9	2013	2	0	0
T10	14910	2	0	0