Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	14649958	34519	0	0
RomAllowCheckGoodState_A	14649958	34565	0	0
RomBlockActiveState_A	14649958	28735	0	0
RomBlockCheckGoodState_A	14649958	324989	0	0
RomIntgChkDisFalse_A	14649958	14206163	0	0
RomIntgChkDisTrue_A	14649958	117833	0	0
RstreqChkEsctimeout_A	14649958	2491	0	0
RstreqChkFsmterm_A	14649958	180	0	0
RstreqChkGlbesc_A	14649958	2492	0	0
RstreqChkMainpd_A	14649958	651519	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	34519	0	0
T1	21141	85	0	0
T2	3321	5	0	0
T3	4005	7	0	0
T4	4869	3	0	0
T5	5466	5	0	0
T6	2693	4	0	0
T7	3281	5	0	0
T8	748	2	0	0
T9	2013	2	0	0
T10	14910	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	34565	0	0
T1	21141	85	0	0
T2	3321	5	0	0
T3	4005	7	0	0
T4	4869	3	0	0
T5	5466	5	0	0
T6	2693	4	0	0
T7	3281	5	0	0
T8	748	2	0	0
T9	2013	2	0	0
T10	14910	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	28735	0	0
T1	21141	16	0	0
T2	3321	0	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T27	0	1376	0	0
T28	0	16	0	0
T37	0	1	0	0
T38	0	1525	0	0
T127	0	232	0	0
T138	0	279	0	0
T139	0	6	0	0
T140	0	210	0	0
T141	0	20	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	324989	0	0
T1	21141	1035	0	0
T2	3321	0	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	0	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T15	0	252	0	0
T22	0	918	0	0
T23	0	1241	0	0
T26	0	2242	0	0
T27	0	582	0	0
T28	0	1257	0	0
T40	0	114	0	0
T128	0	1304	0	0
T138	0	98	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	14206163	0	0
T1	21141	21051	0	0
T2	3321	2921	0	0
T3	4005	3936	0	0
T4	4869	4796	0	0
T5	5466	5368	0	0
T6	2693	2632	0	0
T7	3281	2843	0	0
T8	748	697	0	0
T9	2013	1899	0	0
T10	14910	14847	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	117833	0	0
T11	2419	0	0	0
T12	15579	0	0	0
T17	2969	0	0	0
T26	31761	405	0	0
T27	5453	1497	0	0
T28	18009	1063	0	0
T38	0	507	0	0
T41	1358	0	0	0
T46	1214	0	0	0
T50	3270	0	0	0
T60	1518	0	0	0
T127	0	338	0	0
T128	0	485	0	0
T138	0	904	0	0
T142	0	1222	0	0
T143	0	336	0	0
T144	0	571	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	2491	0	0
T9	2013	1	0	0
T10	14910	1	0	0
T11	2419	1	0	0
T12	15579	1	0	0
T13	2772	4	0	0
T14	3994	7	0	0
T15	0	21	0	0
T17	2969	0	0	0
T26	31761	0	0	0
T27	0	4	0	0
T41	0	1	0	0
T44	3225	0	0	0
T45	4471	0	0	0
T46	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	180	0	0
T19	26998	40	0	0
T20	0	20	0	0
T21	0	40	0	0
T29	0	40	0	0
T30	0	40	0	0
T31	20030	0	0	0
T32	1842	0	0	0
T33	774	0	0	0
T34	15586	0	0	0
T35	5652	0	0	0
T36	2416	0	0	0
T37	23022	0	0	0
T38	5616	0	0	0
T39	1248	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	2492	0	0
T9	2013	1	0	0
T10	14910	1	0	0
T11	2419	1	0	0
T12	15579	1	0	0
T13	2772	4	0	0
T14	3994	7	0	0
T15	0	21	0	0
T17	2969	0	0	0
T26	31761	0	0	0
T27	0	4	0	0
T41	0	1	0	0
T44	3225	0	0	0
T45	4471	0	0	0
T46	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14649958	651519	0	0
T1	21141	1870	0	0
T2	3321	0	0	0
T3	4005	0	0	0
T4	4869	0	0	0
T5	5466	0	0	0
T6	2693	0	0	0
T7	3281	17	0	0
T8	748	0	0	0
T9	2013	0	0	0
T10	14910	0	0	0
T13	0	85	0	0
T14	0	187	0	0
T15	0	1702	0	0
T17	0	24	0	0
T18	0	10	0	0
T26	0	2312	0	0
T27	0	758	0	0
T28	0	1639	0	0