Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	438033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

224292

1

T2

259

T3

64

T4

264

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	429700	1			T1	1		T2	594		T3	111
values[0x0]	115864	1			T2	25		T3	30		T4	231
values[0x1]	116761	1			T2	49		T3	40		T4	221

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	347376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

314949

1

T1

1

T2

334

T3

89

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1945	1			T2	5		T4	5		T6	1
valid_sources[0x01]	2366	1			T4	2		T6	1		T9	1
valid_sources[0x02]	2010	1			T2	5		T4	5		T6	3
valid_sources[0x03]	4094	1			T2	4		T4	1		T53	2
valid_sources[0x04]	2199	1			T2	3		T4	5		T6	1
valid_sources[0x05]	2169	1			T2	2		T4	4		T6	1
valid_sources[0x06]	2065	1			T2	4		T4	8		T9	2
valid_sources[0x07]	1873	1			T2	1		T4	8		T9	20
valid_sources[0x08]	2465	1			T2	1		T4	4		T6	1
valid_sources[0x09]	2171	1			T2	1		T4	4		T6	2
valid_sources[0x0a]	2034	1			T2	6		T4	2		T5	1
valid_sources[0x0b]	1951	1			T2	1		T4	3		T5	3
valid_sources[0x0c]	1811	1			T2	2		T4	2		T6	1
valid_sources[0x0d]	2014	1			T2	4		T4	4		T9	9
valid_sources[0x0e]	3085	1			T2	3		T4	9		T6	2
valid_sources[0x0f]	1865	1			T2	1		T4	3		T5	3
valid_sources[0x10]	2119	1			T2	2		T4	4		T5	2
valid_sources[0x11]	3218	1			T2	1		T4	6		T6	1
valid_sources[0x12]	1870	1			T4	1		T30	2		T14	26
valid_sources[0x13]	2210	1			T2	1		T4	5		T9	2
valid_sources[0x14]	2198	1			T2	2		T4	3		T5	1
valid_sources[0x15]	2779	1			T2	7		T4	8		T5	10
valid_sources[0x16]	2210	1			T2	1		T4	1		T53	1
valid_sources[0x17]	1879	1			T2	3		T4	3		T5	5
valid_sources[0x18]	2289	1			T2	2		T4	3		T53	3
valid_sources[0x19]	1844	1			T2	2		T4	1		T6	1
valid_sources[0x1a]	3627	1			T2	6		T4	6		T5	3
valid_sources[0x1b]	2077	1			T2	7		T4	4		T5	2
valid_sources[0x1c]	14823	1			T2	3		T4	5		T5	1
valid_sources[0x1d]	2133	1			T2	1		T4	2		T57	2
valid_sources[0x1e]	1880	1			T2	1		T4	2		T6	2
valid_sources[0x1f]	2213	1			T2	1		T4	4		T9	5
valid_sources[0x20]	2134	1			T2	3		T4	3		T5	1
valid_sources[0x21]	2325	1			T2	6		T4	3		T5	6
valid_sources[0x22]	2028	1			T2	3		T4	7		T6	1
valid_sources[0x23]	2068	1			T2	5		T4	4		T9	6
valid_sources[0x24]	3496	1			T2	3		T4	4		T5	3
valid_sources[0x25]	2106	1			T2	4		T4	1		T5	2
valid_sources[0x26]	4446	1			T2	3		T4	8		T5	2
valid_sources[0x27]	2293	1			T4	2		T30	5		T14	29
valid_sources[0x28]	2168	1			T2	6		T4	3		T9	18
valid_sources[0x29]	2071	1			T2	4		T4	3		T5	2
valid_sources[0x2a]	2053	1			T2	2		T4	5		T5	5
valid_sources[0x2b]	4135	1			T4	3		T5	2		T6	1
valid_sources[0x2c]	2071	1			T2	1		T4	2		T6	1
valid_sources[0x2d]	2337	1			T2	1		T4	2		T6	1
valid_sources[0x2e]	2023	1			T2	4		T4	7		T9	4
valid_sources[0x2f]	1973	1			T2	3		T4	1		T5	1
valid_sources[0x30]	1935	1			T2	1		T4	3		T9	12
valid_sources[0x31]	2687	1			T2	4		T4	2		T9	28
valid_sources[0x32]	2086	1			T2	4		T4	2		T6	1
valid_sources[0x33]	2082	1			T2	3		T4	5		T5	1
valid_sources[0x34]	1819	1			T2	6		T4	1		T30	15
valid_sources[0x35]	2299	1			T2	2		T4	3		T5	2
valid_sources[0x36]	2020	1			T4	9		T5	3		T9	4
valid_sources[0x37]	1751	1			T2	3		T4	3		T9	2
valid_sources[0x38]	2439	1			T2	2		T4	2		T5	4
valid_sources[0x39]	1726	1			T2	1		T4	3		T6	1
valid_sources[0x3a]	2107	1			T2	3		T4	2		T30	8
valid_sources[0x3b]	5129	1			T2	3		T4	4		T5	2
valid_sources[0x3c]	2003	1			T2	2		T4	1		T9	11
valid_sources[0x3d]	1974	1			T2	1		T4	4		T5	5
valid_sources[0x3e]	2503	1			T2	3		T4	3		T5	2
valid_sources[0x3f]	1882	1			T2	1		T4	6		T5	1
valid_sources[0x40]	1800	1			T2	1		T4	6		T6	3
valid_sources[0x41]	2187	1			T2	2		T4	1		T53	3
valid_sources[0x42]	2016	1			T2	6		T4	7		T5	3
valid_sources[0x43]	1953	1			T2	5		T4	1		T6	1
valid_sources[0x44]	7369	1			T2	1		T4	4		T6	1
valid_sources[0x45]	1993	1			T2	1		T4	1		T10	2
valid_sources[0x46]	2739	1			T2	3		T4	5		T5	2
valid_sources[0x47]	2290	1			T2	2		T4	4		T5	6
valid_sources[0x48]	2110	1			T2	4		T4	7		T5	1
valid_sources[0x49]	2049	1			T2	1		T4	2		T5	1
valid_sources[0x4a]	1981	1			T2	3		T4	1		T6	1
valid_sources[0x4b]	2128	1			T2	5		T9	2		T53	3
valid_sources[0x4c]	14646	1			T2	3		T4	5		T6	2
valid_sources[0x4d]	2043	1			T2	1		T4	5		T30	4
valid_sources[0x4e]	2260	1			T2	1		T5	4		T6	1
valid_sources[0x4f]	3178	1			T2	3		T4	9		T10	5
valid_sources[0x50]	2304	1			T2	4		T4	5		T53	2
valid_sources[0x51]	2228	1			T2	2		T4	5		T5	2
valid_sources[0x52]	2046	1			T2	1		T4	4		T9	3
valid_sources[0x53]	1991	1			T2	2		T4	5		T9	3
valid_sources[0x54]	2034	1			T2	2		T4	7		T5	4
valid_sources[0x55]	1980	1			T2	3		T4	1		T6	1
valid_sources[0x56]	2106	1			T2	1		T4	6		T5	3
valid_sources[0x57]	1888	1			T2	2		T4	2		T53	1
valid_sources[0x58]	2299	1			T2	6		T4	4		T6	3
valid_sources[0x59]	2156	1			T2	5		T4	1		T9	7
valid_sources[0x5a]	2125	1			T2	3		T4	2		T5	1
valid_sources[0x5b]	1845	1			T2	3		T4	2		T5	1
valid_sources[0x5c]	2030	1			T2	1		T5	2		T9	18
valid_sources[0x5d]	2274	1			T2	3		T4	3		T9	20
valid_sources[0x5e]	2120	1			T2	5		T4	7		T6	1
valid_sources[0x5f]	3965	1			T2	2		T4	2		T6	3
valid_sources[0x60]	2270	1			T2	5		T4	3		T5	2
valid_sources[0x61]	2022	1			T2	3		T4	2		T5	3
valid_sources[0x62]	2073	1			T2	4		T4	3		T9	3
valid_sources[0x63]	1989	1			T2	4		T4	3		T9	3
valid_sources[0x64]	2048	1			T2	2		T4	5		T6	1
valid_sources[0x65]	1997	1			T2	4		T4	5		T6	1
valid_sources[0x66]	2044	1			T2	2		T4	7		T6	1
valid_sources[0x67]	2122	1			T2	2		T4	6		T6	2
valid_sources[0x68]	2263	1			T2	1		T4	3		T5	5
valid_sources[0x69]	2092	1			T2	4		T4	5		T5	1
valid_sources[0x6a]	2151	1			T2	1		T4	5		T30	8
valid_sources[0x6b]	1988	1			T2	1		T4	6		T6	1
valid_sources[0x6c]	8585	1			T2	2		T4	4		T5	1
valid_sources[0x6d]	2002	1			T2	2		T4	6		T9	12
valid_sources[0x6e]	2175	1			T2	2		T4	6		T6	2
valid_sources[0x6f]	15145	1			T2	3		T4	1		T6	1
valid_sources[0x70]	2123	1			T2	3		T4	6		T6	1
valid_sources[0x71]	1981	1			T2	3		T4	5		T5	1
valid_sources[0x72]	2136	1			T2	2		T4	6		T6	1
valid_sources[0x73]	2000	1			T2	1		T4	2		T9	4
valid_sources[0x74]	1969	1			T2	1		T4	4		T5	2
valid_sources[0x75]	1912	1			T2	1		T4	2		T30	7
valid_sources[0x76]	1912	1			T2	2		T4	4		T5	5
valid_sources[0x77]	2987	1			T2	2		T4	4		T6	1
valid_sources[0x78]	2075	1			T2	1		T4	5		T6	1
valid_sources[0x79]	2036	1			T2	2		T4	7		T6	3
valid_sources[0x7a]	2063	1			T2	4		T4	2		T9	7
valid_sources[0x7b]	2032	1			T2	4		T4	6		T9	5
valid_sources[0x7c]	2129	1			T2	5		T4	5		T5	1
valid_sources[0x7d]	1894	1			T2	1		T4	6		T9	2
valid_sources[0x7e]	2091	1			T2	4		T4	2		T9	5
valid_sources[0x7f]	1877	1			T2	3		T4	11		T5	2
valid_sources[0x80]	1908	1			T2	3		T4	5		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

155763

1

T2

240

T3

47

T4

138

values[0x0]

all_enables

biggest_size

44026

1

T2

10

T3

9

T4

90

values[0x1]

all_enables

biggest_size

24503

1

T2

9

T3

8

T4

36