SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35300 | 1 | T4 | 401 | T9 | 320 | T72 | 420 | ||||
others[1] | 34878 | 1 | T4 | 392 | T9 | 324 | T72 | 405 | ||||
others[2] | 35182 | 1 | T4 | 419 | T9 | 288 | T72 | 408 | ||||
others[3] | 57970 | 1 | T4 | 660 | T9 | 472 | T72 | 637 | ||||
false | 14215 | 1 | T4 | 50 | T9 | 50 | T30 | 66 | ||||
true | 22239 | 1 | T1 | 3 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34965 | 1 | T4 | 418 | T9 | 323 | T28 | 1 | ||||
others[1] | 34866 | 1 | T4 | 378 | T9 | 292 | T72 | 420 | ||||
others[2] | 35335 | 1 | T4 | 396 | T9 | 302 | T72 | 388 | ||||
others[3] | 58237 | 1 | T4 | 653 | T9 | 494 | T72 | 676 | ||||
false | 9698 | 1 | T4 | 50 | T9 | 50 | T30 | 33 | ||||
true | 17769 | 1 | T1 | 3 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 482 | 1 | T8 | 1 | T42 | 1 | T135 | 5 | ||||
others[1] | 472 | 1 | T41 | 1 | T30 | 1 | T135 | 4 | ||||
others[2] | 536 | 1 | T5 | 1 | T8 | 1 | T41 | 1 | ||||
others[3] | 831 | 1 | T2 | 2 | T5 | 3 | T8 | 2 | ||||
false | 9251 | 1 | T1 | 3 | T2 | 14 | T3 | 1 | ||||
true | 2524 | 1 | T2 | 10 | T5 | 6 | T8 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |