Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T10,T30

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	18379833	4747	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	18379833	206906	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	18379833	7420252	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	18379833	206900	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	18379833	4747	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	18379833	206906	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	18379833	7420252	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	18379833	206900	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	4747	0	0
T4	23628	22	0	0
T5	5498	0	0	0
T6	12026	0	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	15	0	0
T10	2823	2	0	0
T14	0	6	0	0
T16	0	9	0	0
T25	0	75	0	0
T29	0	22	0	0
T30	0	16	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T53	6744	0	0	0
T72	0	16	0	0
T73	0	8	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	206906	0	0
T4	23628	603	0	0
T5	5498	0	0	0
T6	12026	0	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	439	0	0
T10	2823	361	0	0
T14	0	476	0	0
T16	0	214	0	0
T25	0	3759	0	0
T29	0	1544	0	0
T30	0	1376	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T53	6744	0	0	0
T72	0	421	0	0
T73	0	166	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	7420252	0	0
T3	2564	1338	0	0
T4	23628	10369	0	0
T5	5498	0	0	0
T6	12026	4505	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	11421	0	0
T10	2823	266	0	0
T14	0	69750	0	0
T30	0	27878	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T53	0	4107	0	0
T57	0	1593	0	0
T72	0	11006	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	206900	0	0
T4	23628	603	0	0
T5	5498	0	0	0
T6	12026	0	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	439	0	0
T10	2823	361	0	0
T14	0	476	0	0
T16	0	214	0	0
T25	0	3761	0	0
T29	0	1544	0	0
T30	0	1376	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T53	6744	0	0	0
T72	0	421	0	0
T73	0	166	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	4747	0	0
T4	23628	22	0	0
T5	5498	0	0	0
T6	12026	0	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	15	0	0
T10	2823	2	0	0
T14	0	6	0	0
T16	0	9	0	0
T25	0	75	0	0
T29	0	22	0	0
T30	0	16	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T53	6744	0	0	0
T72	0	16	0	0
T73	0	8	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	206906	0	0
T4	23628	603	0	0
T5	5498	0	0	0
T6	12026	0	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	439	0	0
T10	2823	361	0	0
T14	0	476	0	0
T16	0	214	0	0
T25	0	3759	0	0
T29	0	1544	0	0
T30	0	1376	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T53	6744	0	0	0
T72	0	421	0	0
T73	0	166	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	7420252	0	0
T3	2564	1338	0	0
T4	23628	10369	0	0
T5	5498	0	0	0
T6	12026	4505	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	11421	0	0
T10	2823	266	0	0
T14	0	69750	0	0
T30	0	27878	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T53	0	4107	0	0
T57	0	1593	0	0
T72	0	11006	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	206900	0	0
T4	23628	603	0	0
T5	5498	0	0	0
T6	12026	0	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	439	0	0
T10	2823	361	0	0
T14	0	476	0	0
T16	0	214	0	0
T25	0	3761	0	0
T29	0	1544	0	0
T30	0	1376	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T53	6744	0	0	0
T72	0	421	0	0
T73	0	166	0	0