Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18958202	12861	0	0
intr_enable_rd_A	18958202	23470	0	0
reset_en_rd_A	18958202	1482	0	0
reset_en_regwen_rd_A	18958202	1214	0	0
wake_info_capture_dis_rd_A	18958202	1107	0	0
wakeup_en_rd_A	18958202	2412	0	0
wakeup_en_regwen_rd_A	18958202	1243	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18958202	12861	0	0
T12	15469	0	0	0
T17	2116	0	0	0
T25	303124	96	0	0
T26	0	52	0	0
T27	0	11	0	0
T50	0	4	0	0
T51	0	10	0	0
T52	0	432	0	0
T54	0	715	0	0
T56	0	223	0	0
T58	2048	0	0	0
T76	0	34	0	0
T79	0	1	0	0
T111	864	0	0	0
T112	7080	0	0	0
T113	2044	0	0	0
T114	1062	0	0	0
T115	2618	0	0	0
T116	7430	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18958202	23470	0	0
T5	5498	18	0	0
T6	12026	50	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	0	0	0
T10	2823	0	0	0
T28	0	25	0	0
T41	2822	0	0	0
T45	1376	0	0	0
T49	0	19	0	0
T53	6744	42	0	0
T57	2537	1	0	0
T72	0	193	0	0
T114	0	4	0	0
T117	0	8	0	0
T118	0	3	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18958202	1482	0	0
T50	1011	6	0	0
T51	8153	0	0	0
T52	2841	0	0	0
T54	3469	0	0	0
T55	0	53	0	0
T60	3597	48	0	0
T63	1785	0	0	0
T64	1421	0	0	0
T68	0	69	0	0
T70	0	107	0	0
T76	3302	0	0	0
T77	1717	9	0	0
T78	1666	0	0	0
T83	0	10	0	0
T86	0	10	0	0
T87	0	50	0	0
T88	0	36	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18958202	1214	0	0
T50	1011	0	0	0
T51	8153	0	0	0
T52	2841	0	0	0
T54	3469	0	0	0
T55	0	32	0	0
T60	3597	25	0	0
T63	1785	0	0	0
T64	1421	0	0	0
T68	0	62	0	0
T70	0	79	0	0
T76	3302	0	0	0
T77	1717	0	0	0
T78	1666	0	0	0
T83	0	16	0	0
T86	0	6	0	0
T87	0	55	0	0
T88	0	29	0	0
T108	0	17	0	0
T119	0	46	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18958202	1107	0	0
T50	1011	12	0	0
T51	8153	0	0	0
T52	2841	0	0	0
T54	3469	0	0	0
T55	0	30	0	0
T60	3597	55	0	0
T63	1785	0	0	0
T64	1421	0	0	0
T68	0	14	0	0
T70	0	68	0	0
T76	3302	0	0	0
T77	1717	9	0	0
T78	1666	0	0	0
T83	0	4	0	0
T87	0	45	0	0
T88	0	26	0	0
T108	0	20	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18958202	2412	0	0
T50	1011	11	0	0
T51	8153	0	0	0
T52	2841	0	0	0
T54	3469	0	0	0
T55	0	221	0	0
T60	3597	59	0	0
T63	1785	0	0	0
T64	1421	0	0	0
T68	0	115	0	0
T70	0	228	0	0
T76	3302	0	0	0
T77	1717	41	0	0
T78	1666	0	0	0
T83	0	17	0	0
T86	0	16	0	0
T87	0	59	0	0
T88	0	44	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18958202	1243	0	0
T50	1011	2	0	0
T51	8153	0	0	0
T52	2841	0	0	0
T54	3469	0	0	0
T55	0	29	0	0
T60	3597	21	0	0
T63	1785	0	0	0
T64	1421	0	0	0
T68	0	28	0	0
T70	0	70	0	0
T76	3302	0	0	0
T77	1717	6	0	0
T78	1666	0	0	0
T83	0	12	0	0
T87	0	65	0	0
T88	0	5	0	0
T108	0	12	0	0