Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	18379833	37080	0	0
IoStatusRise_A	18379833	41173	0	0
MainStatusFall_A	18379833	37080	0	0
MainStatusRise_A	18379833	41173	0	0
UsbStatusFall_A	18379833	27728	0	0
UsbStatusRise_A	18379833	31137	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	37080	0	0
T2	7209	23	0	0
T3	2564	7	0	0
T4	23628	83	0	0
T5	5498	20	0	0
T6	12026	11	0	0
T7	1721	0	0	0
T8	8048	18	0	0
T9	29770	80	0	0
T10	2823	4	0	0
T41	2822	18	0	0
T53	0	11	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	41173	0	0
T1	2458	3	0	0
T2	7209	25	0	0
T3	2564	8	0	0
T4	23628	85	0	0
T5	5498	22	0	0
T6	12026	12	0	0
T7	1721	6	0	0
T8	8048	20	0	0
T9	29770	81	0	0
T10	2823	5	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	37080	0	0
T2	7209	23	0	0
T3	2564	7	0	0
T4	23628	83	0	0
T5	5498	20	0	0
T6	12026	11	0	0
T7	1721	0	0	0
T8	8048	18	0	0
T9	29770	80	0	0
T10	2823	4	0	0
T41	2822	18	0	0
T53	0	11	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	41173	0	0
T1	2458	3	0	0
T2	7209	25	0	0
T3	2564	8	0	0
T4	23628	85	0	0
T5	5498	22	0	0
T6	12026	12	0	0
T7	1721	6	0	0
T8	8048	20	0	0
T9	29770	81	0	0
T10	2823	5	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	27728	0	0
T2	7209	23	0	0
T3	2564	6	0	0
T4	23628	53	0	0
T5	5498	20	0	0
T6	12026	10	0	0
T7	1721	0	0	0
T8	8048	18	0	0
T9	29770	42	0	0
T10	2823	4	0	0
T41	2822	18	0	0
T53	0	9	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	31137	0	0
T1	2458	3	0	0
T2	7209	25	0	0
T3	2564	6	0	0
T4	23628	55	0	0
T5	5498	22	0	0
T6	12026	11	0	0
T7	1721	6	0	0
T8	8048	20	0	0
T9	29770	42	0	0
T10	2823	5	0	0