Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.51	100.00	83.33	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	18379833	40798	0	0
RomAllowCheckGoodState_A	18379833	40848	0	0
RomBlockActiveState_A	18379833	31075	0	0
RomBlockCheckGoodState_A	18379833	361234	0	0
RomIntgChkDisFalse_A	18379833	17875536	0	0
RomIntgChkDisTrue_A	18379833	131083	0	0
RstreqChkEsctimeout_A	18379833	2701	0	0
RstreqChkFsmterm_A	18379833	140	0	0
RstreqChkGlbesc_A	18379833	2702	0	0
RstreqChkMainpd_A	18379833	774044	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	40798	0	0
T1	2458	3	0	0
T2	7209	25	0	0
T3	2564	8	0	0
T4	23628	85	0	0
T5	5498	22	0	0
T6	12026	12	0	0
T7	1721	6	0	0
T8	8048	13	0	0
T9	29770	81	0	0
T10	2823	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	40848	0	0
T1	2458	3	0	0
T2	7209	25	0	0
T3	2564	8	0	0
T4	23628	85	0	0
T5	5498	22	0	0
T6	12026	12	0	0
T7	1721	6	0	0
T8	8048	14	0	0
T9	29770	81	0	0
T10	2823	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	31075	0	0
T28	1522	120	0	0
T43	1415	229	0	0
T44	2780	0	0	0
T49	0	213	0	0
T73	7370	0	0	0
T113	0	176	0	0
T117	1542	0	0	0
T118	3959	0	0	0
T120	0	1330	0	0
T121	0	4	0	0
T122	0	450	0	0
T123	0	180	0	0
T124	0	14	0	0
T125	0	295	0	0
T126	2061	0	0	0
T127	6823	0	0	0
T128	2398	0	0	0
T129	16960	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	361234	0	0
T4	23628	1278	0	0
T5	5498	0	0	0
T6	12026	0	0	0
T7	1721	0	0	0
T8	8048	0	0	0
T9	29770	2266	0	0
T10	2823	0	0	0
T14	0	115	0	0
T16	0	597	0	0
T29	0	4071	0	0
T30	0	757	0	0
T41	2822	0	0	0
T43	0	55	0	0
T45	1376	0	0	0
T49	0	78	0	0
T53	6744	0	0	0
T72	0	1339	0	0
T73	0	460	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	17875536	0	0
T1	2458	2227	0	0
T2	7209	7076	0	0
T3	2564	2490	0	0
T4	23628	23453	0	0
T5	5498	5368	0	0
T6	12026	11957	0	0
T7	1721	1244	0	0
T8	8048	7103	0	0
T9	29770	28658	0	0
T10	2823	2487	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	131083	0	0
T9	29770	1042	0	0
T10	2823	0	0	0
T23	2299	0	0	0
T24	3053	0	0	0
T28	0	193	0	0
T29	0	1223	0	0
T30	65378	0	0	0
T41	2822	0	0	0
T42	4444	0	0	0
T43	0	589	0	0
T45	1376	0	0	0
T53	6744	0	0	0
T57	2537	0	0	0
T113	0	1043	0	0
T122	0	186	0	0
T123	0	383	0	0
T130	0	2716	0	0
T131	0	3095	0	0
T132	0	2259	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	2701	0	0
T1	2458	2	0	0
T2	7209	15	0	0
T3	2564	0	0	0
T4	23628	0	0	0
T5	5498	10	0	0
T6	12026	0	0	0
T7	1721	5	0	0
T8	8048	9	0	0
T9	29770	0	0	0
T10	2823	0	0	0
T23	0	4	0	0
T30	0	5	0	0
T41	0	6	0	0
T42	0	7	0	0
T45	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	140	0	0
T20	45452	40	0	0
T21	0	20	0	0
T22	0	20	0	0
T26	187395	0	0	0
T31	0	40	0	0
T32	0	20	0	0
T33	6710	0	0	0
T34	815	0	0	0
T35	7004	0	0	0
T36	1032	0	0	0
T37	15198	0	0	0
T38	996	0	0	0
T39	3868	0	0	0
T40	787	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	2702	0	0
T1	2458	2	0	0
T2	7209	15	0	0
T3	2564	0	0	0
T4	23628	0	0	0
T5	5498	10	0	0
T6	12026	0	0	0
T7	1721	5	0	0
T8	8048	9	0	0
T9	29770	0	0	0
T10	2823	0	0	0
T23	0	4	0	0
T30	0	5	0	0
T41	0	6	0	0
T42	0	7	0	0
T45	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18379833	774044	0	0
T2	7209	679	0	0
T3	2564	0	0	0
T4	23628	2019	0	0
T5	5498	316	0	0
T6	12026	0	0	0
T7	1721	0	0	0
T8	8048	110	0	0
T9	29770	1534	0	0
T10	2823	0	0	0
T24	0	11	0	0
T28	0	31	0	0
T30	0	2908	0	0
T41	2822	80	0	0
T42	0	112	0	0