Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	544396	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

291105

1

T2

1

T3

259

T4

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	563979	1			T1	1		T2	1		T3	481
values[0x0]	135027	1			T3	233		T4	67		T5	27
values[0x1]	136495	1			T3	219		T4	66		T5	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	430833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

404668

1

T2

1

T3

421

T4

77

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2585	1			T3	8		T9	164		T20	2
valid_sources[0x01]	2334	1			T3	3		T6	1		T9	86
valid_sources[0x02]	3685	1			T3	4		T9	139		T39	3
valid_sources[0x03]	2447	1			T3	3		T9	85		T20	2
valid_sources[0x04]	11618	1			T3	4		T6	1		T9	93
valid_sources[0x05]	2264	1			T3	3		T4	1		T6	4
valid_sources[0x06]	2417	1			T3	2		T5	2		T6	2
valid_sources[0x07]	4129	1			T3	6		T6	3		T9	100
valid_sources[0x08]	2292	1			T3	7		T9	79		T20	2
valid_sources[0x09]	2453	1			T3	5		T6	1		T9	83
valid_sources[0x0a]	2546	1			T3	2		T6	2		T9	94
valid_sources[0x0b]	2136	1			T3	4		T4	7		T6	2
valid_sources[0x0c]	2713	1			T3	2		T6	2		T9	106
valid_sources[0x0d]	2266	1			T3	3		T9	144		T20	1
valid_sources[0x0e]	5426	1			T3	4		T6	3		T9	97
valid_sources[0x0f]	2379	1			T3	2		T5	5		T9	130
valid_sources[0x10]	2271	1			T3	4		T6	1		T9	43
valid_sources[0x11]	2129	1			T3	1		T9	75		T39	1
valid_sources[0x12]	2443	1			T3	3		T9	63		T10	2
valid_sources[0x13]	2834	1			T3	9		T9	88		T20	3
valid_sources[0x14]	7723	1			T3	2		T4	3		T6	1
valid_sources[0x15]	2343	1			T3	5		T6	1		T9	72
valid_sources[0x16]	3415	1			T3	3		T9	83		T19	1058
valid_sources[0x17]	2612	1			T3	5		T9	62		T10	5
valid_sources[0x18]	2378	1			T3	6		T9	96		T20	2
valid_sources[0x19]	3870	1			T3	9		T6	3		T9	64
valid_sources[0x1a]	2824	1			T3	4		T9	118		T20	4
valid_sources[0x1b]	2286	1			T3	5		T4	1		T9	117
valid_sources[0x1c]	2378	1			T3	2		T9	131		T39	1
valid_sources[0x1d]	2224	1			T3	3		T9	66		T20	8
valid_sources[0x1e]	2197	1			T3	5		T6	1		T9	67
valid_sources[0x1f]	2798	1			T3	1		T6	1		T9	104
valid_sources[0x20]	2361	1			T3	2		T4	1		T9	130
valid_sources[0x21]	10725	1			T3	3		T6	2		T9	90
valid_sources[0x22]	2575	1			T3	3		T9	129		T20	3
valid_sources[0x23]	2370	1			T3	5		T9	148		T10	1
valid_sources[0x24]	2661	1			T3	2		T4	1		T9	97
valid_sources[0x25]	4310	1			T3	1		T9	99		T20	2
valid_sources[0x26]	2517	1			T3	3		T5	8		T6	1
valid_sources[0x27]	2291	1			T3	4		T4	6		T9	71
valid_sources[0x28]	4382	1			T3	1		T9	155		T39	2
valid_sources[0x29]	2454	1			T3	6		T6	2		T9	80
valid_sources[0x2a]	3475	1			T3	3		T6	1		T9	133
valid_sources[0x2b]	2678	1			T3	1		T9	78		T10	3
valid_sources[0x2c]	2738	1			T3	2		T9	110		T10	1
valid_sources[0x2d]	2982	1			T3	3		T6	2		T9	104
valid_sources[0x2e]	6308	1			T3	1		T4	11		T9	77
valid_sources[0x2f]	2436	1			T3	3		T6	1		T9	66
valid_sources[0x30]	2503	1			T3	3		T9	45		T39	1
valid_sources[0x31]	12258	1			T3	4		T6	3		T9	88
valid_sources[0x32]	2634	1			T4	6		T6	1		T9	154
valid_sources[0x33]	2356	1			T3	3		T6	2		T9	111
valid_sources[0x34]	2781	1			T3	2		T5	1		T6	1
valid_sources[0x35]	2746	1			T3	3		T9	106		T39	2
valid_sources[0x36]	2453	1			T3	2		T9	116		T10	4
valid_sources[0x37]	5992	1			T3	2		T5	2		T9	102
valid_sources[0x38]	3486	1			T3	3		T9	93		T10	2
valid_sources[0x39]	2802	1			T3	2		T4	1		T9	127
valid_sources[0x3a]	2583	1			T3	5		T9	128		T20	4
valid_sources[0x3b]	2691	1			T3	4		T6	1		T9	136
valid_sources[0x3c]	2587	1			T3	3		T5	11		T9	110
valid_sources[0x3d]	2840	1			T3	9		T9	72		T20	1
valid_sources[0x3e]	3558	1			T3	4		T6	1		T9	106
valid_sources[0x3f]	6050	1			T3	3		T5	4		T9	142
valid_sources[0x40]	2608	1			T3	4		T9	118		T20	9
valid_sources[0x41]	2773	1			T3	4		T9	228		T39	2
valid_sources[0x42]	2310	1			T3	3		T9	150		T39	4
valid_sources[0x43]	2270	1			T3	4		T9	76		T39	2
valid_sources[0x44]	2533	1			T3	3		T9	93		T39	2
valid_sources[0x45]	3081	1			T3	3		T6	1		T9	129
valid_sources[0x46]	2743	1			T3	8		T6	3		T9	179
valid_sources[0x47]	8841	1			T3	6		T5	2		T9	122
valid_sources[0x48]	2650	1			T3	3		T6	1		T9	146
valid_sources[0x49]	2445	1			T3	1		T6	1		T9	110
valid_sources[0x4a]	3011	1			T3	4		T6	1		T9	103
valid_sources[0x4b]	2455	1			T3	5		T6	1		T9	129
valid_sources[0x4c]	2606	1			T3	6		T6	2		T9	93
valid_sources[0x4d]	3433	1			T3	2		T9	99		T39	2
valid_sources[0x4e]	2485	1			T3	3		T6	5		T9	93
valid_sources[0x4f]	4035	1			T3	1		T4	6		T6	1
valid_sources[0x50]	2623	1			T3	7		T9	101		T39	1
valid_sources[0x51]	2771	1			T3	1		T5	1		T6	3
valid_sources[0x52]	2551	1			T3	1		T9	115		T39	2
valid_sources[0x53]	2399	1			T3	4		T6	2		T9	66
valid_sources[0x54]	2611	1			T3	4		T9	121		T20	4
valid_sources[0x55]	2573	1			T3	4		T9	72		T39	4
valid_sources[0x56]	2800	1			T3	1		T6	1		T9	58
valid_sources[0x57]	2689	1			T3	1		T5	7		T6	1
valid_sources[0x58]	6489	1			T3	2		T9	125		T39	4
valid_sources[0x59]	7706	1			T3	5		T5	1		T6	2
valid_sources[0x5a]	2234	1			T3	3		T9	71		T39	1
valid_sources[0x5b]	2247	1			T3	2		T9	82		T10	2
valid_sources[0x5c]	2231	1			T3	5		T6	1		T9	69
valid_sources[0x5d]	2759	1			T3	5		T6	1		T9	136
valid_sources[0x5e]	3076	1			T3	2		T6	1		T9	64
valid_sources[0x5f]	2563	1			T3	5		T4	7		T9	94
valid_sources[0x60]	2191	1			T3	2		T4	1		T5	1
valid_sources[0x61]	2694	1			T3	4		T9	72		T20	10
valid_sources[0x62]	2301	1			T3	4		T5	1		T9	108
valid_sources[0x63]	2324	1			T3	2		T9	110		T39	1
valid_sources[0x64]	2679	1			T3	1		T6	1		T9	66
valid_sources[0x65]	3622	1			T3	2		T6	1		T9	156
valid_sources[0x66]	2632	1			T3	9		T5	2		T9	161
valid_sources[0x67]	2482	1			T3	3		T9	94		T39	1
valid_sources[0x68]	2369	1			T3	4		T9	144		T10	3
valid_sources[0x69]	2253	1			T3	8		T9	76		T10	2
valid_sources[0x6a]	2340	1			T3	6		T5	3		T9	86
valid_sources[0x6b]	2512	1			T9	100		T34	3		T36	12
valid_sources[0x6c]	2385	1			T3	5		T9	161		T20	2
valid_sources[0x6d]	2552	1			T3	1		T6	2		T9	123
valid_sources[0x6e]	2325	1			T3	5		T9	158		T39	1
valid_sources[0x6f]	2930	1			T3	1		T9	115		T39	1
valid_sources[0x70]	2408	1			T3	2		T4	12		T5	8
valid_sources[0x71]	2425	1			T3	4		T4	3		T9	125
valid_sources[0x72]	7495	1			T3	4		T6	2		T9	116
valid_sources[0x73]	2308	1			T3	9		T6	2		T8	1
valid_sources[0x74]	3143	1			T3	1		T9	104		T39	1
valid_sources[0x75]	2434	1			T3	5		T9	54		T39	1
valid_sources[0x76]	2432	1			T3	3		T9	114		T39	1
valid_sources[0x77]	2381	1			T3	4		T6	1		T9	95
valid_sources[0x78]	2416	1			T3	3		T9	128		T10	3
valid_sources[0x79]	2504	1			T3	3		T9	99		T39	1
valid_sources[0x7a]	5740	1			T3	2		T6	1		T9	125
valid_sources[0x7b]	2537	1			T3	6		T9	124		T20	3
valid_sources[0x7c]	2224	1			T3	3		T6	1		T9	163
valid_sources[0x7d]	2765	1			T3	4		T4	2		T9	92
valid_sources[0x7e]	4004	1			T3	6		T5	3		T9	101
valid_sources[0x7f]	2700	1			T3	6		T4	8		T9	126
valid_sources[0x80]	2320	1			T3	5		T5	7		T9	99

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

211824

1

T2

1

T3

129

T5

20

values[0x0]

all_enables

biggest_size

50759

1

T3

87

T4

29

T5

12

values[0x1]

all_enables

biggest_size

28522

1

T3

43

T4

11

T5

2