SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35105 | 1 | T3 | 391 | T19 | 427 | T20 | 305 | ||||
others[1] | 34969 | 1 | T3 | 406 | T19 | 381 | T20 | 289 | ||||
others[2] | 35022 | 1 | T3 | 432 | T19 | 380 | T20 | 310 | ||||
others[3] | 58378 | 1 | T3 | 656 | T19 | 656 | T20 | 502 | ||||
false | 15876 | 1 | T3 | 50 | T6 | 3 | T9 | 412 | ||||
true | 24791 | 1 | T1 | 7 | T2 | 3 | T3 | 101 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35039 | 1 | T3 | 439 | T19 | 384 | T20 | 300 | ||||
others[1] | 35036 | 1 | T3 | 397 | T19 | 387 | T20 | 309 | ||||
others[2] | 35060 | 1 | T3 | 395 | T19 | 409 | T20 | 296 | ||||
others[3] | 58370 | 1 | T3 | 631 | T6 | 1 | T19 | 688 | ||||
false | 10539 | 1 | T3 | 50 | T6 | 3 | T9 | 206 | ||||
true | 19506 | 1 | T1 | 7 | T2 | 3 | T3 | 101 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 621 | 1 | T6 | 1 | T9 | 8 | T39 | 8 | ||||
others[1] | 541 | 1 | T5 | 1 | T9 | 5 | T33 | 1 | ||||
others[2] | 590 | 1 | T5 | 1 | T6 | 1 | T9 | 9 | ||||
others[3] | 1017 | 1 | T9 | 13 | T33 | 1 | T39 | 9 | ||||
false | 11150 | 1 | T1 | 7 | T2 | 3 | T3 | 1 | ||||
true | 3115 | 1 | T5 | 7 | T6 | 2 | T9 | 66 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |