Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22235634	14989	0	0
intr_enable_rd_A	22235634	15803	0	0
reset_en_rd_A	22235634	1487	0	0
reset_en_regwen_rd_A	22235634	1368	0	0
wake_info_capture_dis_rd_A	22235634	1374	0	0
wakeup_en_rd_A	22235634	1874	0	0
wakeup_en_regwen_rd_A	22235634	1244	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22235634	14989	0	0
T9	583031	178	0	0
T10	2539	0	0	0
T11	2318	0	0	0
T17	0	85	0	0
T18	0	27	0	0
T19	47977	0	0	0
T20	54985	0	0	0
T33	6780	0	0	0
T38	1783	0	0	0
T39	3559	0	0	0
T45	0	6	0	0
T46	0	5	0	0
T47	0	528	0	0
T48	0	422	0	0
T49	1378	0	0	0
T51	0	1032	0	0
T74	0	8	0	0
T75	0	317	0	0
T77	2611	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22235634	15803	0	0
T3	18460	92	0	0
T4	1357	0	0	0
T5	2787	0	0	0
T6	5072	0	0	0
T7	2384	0	0	0
T8	2410	0	0	0
T9	583031	0	0	0
T10	2539	43	0	0
T19	47977	216	0	0
T33	6780	0	0	0
T34	0	336	0	0
T39	0	64	0	0
T52	0	23	0	0
T71	0	44	0	0
T73	0	48	0	0
T107	0	62	0	0
T108	0	41	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22235634	1487	0	0
T45	9998	136	0	0
T55	30900	424	0	0
T57	11631	45	0	0
T65	1520	10	0	0
T76	2188	0	0	0
T79	2040	0	0	0
T80	1166	0	0	0
T81	1201	0	0	0
T82	902	0	0	0
T83	1669	0	0	0
T84	0	101	0	0
T85	0	18	0	0
T87	0	58	0	0
T102	0	23	0	0
T109	0	5	0	0
T110	0	10	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22235634	1368	0	0
T45	9998	91	0	0
T55	30900	484	0	0
T57	11631	10	0	0
T65	1520	6	0	0
T76	2188	0	0	0
T79	2040	0	0	0
T80	1166	0	0	0
T81	1201	0	0	0
T82	902	0	0	0
T83	1669	0	0	0
T84	0	118	0	0
T85	0	5	0	0
T87	0	15	0	0
T102	0	19	0	0
T109	0	15	0	0
T110	0	22	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22235634	1374	0	0
T45	9998	72	0	0
T55	30900	420	0	0
T57	11631	9	0	0
T65	1520	9	0	0
T76	2188	0	0	0
T79	2040	0	0	0
T80	1166	0	0	0
T81	1201	0	0	0
T82	902	0	0	0
T83	1669	0	0	0
T84	0	89	0	0
T85	0	18	0	0
T87	0	17	0	0
T102	0	15	0	0
T109	0	15	0	0
T110	0	52	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22235634	1874	0	0
T45	9998	270	0	0
T55	30900	442	0	0
T57	11631	23	0	0
T65	1520	3	0	0
T76	2188	0	0	0
T79	2040	0	0	0
T80	1166	0	0	0
T81	1201	0	0	0
T82	902	0	0	0
T83	1669	0	0	0
T84	0	106	0	0
T85	0	10	0	0
T87	0	12	0	0
T102	0	13	0	0
T109	0	34	0	0
T110	0	31	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22235634	1244	0	0
T45	9998	69	0	0
T55	30900	401	0	0
T57	11631	14	0	0
T65	1520	4	0	0
T76	2188	0	0	0
T79	2040	0	0	0
T80	1166	0	0	0
T81	1201	0	0	0
T82	902	0	0	0
T83	1669	0	0	0
T84	0	100	0	0
T85	0	5	0	0
T87	0	36	0	0
T102	0	14	0	0
T109	0	15	0	0
T110	0	17	0	0