Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	21647678	48389	0	0
RomAllowCheckGoodState_A	21647678	48439	0	0
RomBlockActiveState_A	21647678	29663	0	0
RomBlockCheckGoodState_A	21647678	401984	0	0
RomIntgChkDisFalse_A	21647678	21072281	0	0
RomIntgChkDisTrue_A	21647678	134806	0	0
RstreqChkEsctimeout_A	21647678	3438	0	0
RstreqChkFsmterm_A	21647678	140	0	0
RstreqChkGlbesc_A	21647678	3441	0	0
RstreqChkMainpd_A	21647678	892043	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	48389	0	0
T1	3599	7	0	0
T2	1084	3	0	0
T3	18460	83	0	0
T4	1357	20	0	0
T5	2787	14	0	0
T6	5072	8	0	0
T7	2384	3	0	0
T8	2410	3	0	0
T9	583031	1130	0	0
T10	2539	16	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	48439	0	0
T1	3599	7	0	0
T2	1084	3	0	0
T3	18460	83	0	0
T4	1357	20	0	0
T5	2787	14	0	0
T6	5072	8	0	0
T7	2384	3	0	0
T8	2410	3	0	0
T9	583031	1130	0	0
T10	2539	16	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	29663	0	0
T6	5072	1337	0	0
T7	2384	0	0	0
T8	2410	0	0	0
T9	583031	0	0	0
T10	2539	0	0	0
T11	2318	0	0	0
T19	47977	0	0	0
T22	0	712	0	0
T33	6780	0	0	0
T38	1783	0	0	0
T39	3559	0	0	0
T111	0	9	0	0
T112	0	59	0	0
T113	0	1405	0	0
T114	0	715	0	0
T115	0	74	0	0
T116	0	1151	0	0
T117	0	299	0	0
T118	0	1093	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	401984	0	0
T3	18460	781	0	0
T4	1357	0	0	0
T5	2787	0	0	0
T6	5072	838	0	0
T7	2384	0	0	0
T8	2410	0	0	0
T9	583031	4721	0	0
T10	2539	0	0	0
T17	0	2312	0	0
T19	47977	3081	0	0
T20	0	4007	0	0
T33	6780	0	0	0
T34	0	138	0	0
T36	0	1103	0	0
T71	0	434	0	0
T119	0	436	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	21072281	0	0
T1	3599	3130	0	0
T2	1084	887	0	0
T3	18460	18389	0	0
T4	1357	1307	0	0
T5	2787	2640	0	0
T6	5072	4718	0	0
T7	2384	2263	0	0
T8	2410	2232	0	0
T9	583031	574855	0	0
T10	2539	2465	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	134806	0	0
T6	5072	269	0	0
T7	2384	0	0	0
T8	2410	0	0	0
T9	583031	0	0	0
T10	2539	0	0	0
T11	2318	0	0	0
T19	47977	0	0	0
T20	0	2538	0	0
T21	0	362	0	0
T22	0	95	0	0
T33	6780	0	0	0
T38	1783	0	0	0
T39	3559	0	0	0
T112	0	245	0	0
T113	0	1197	0	0
T114	0	195	0	0
T115	0	141	0	0
T116	0	1773	0	0
T120	0	1105	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	3438	0	0
T5	2787	5	0	0
T6	5072	3	0	0
T7	2384	1	0	0
T8	2410	1	0	0
T9	583031	71	0	0
T10	2539	0	0	0
T11	0	1	0	0
T19	47977	0	0	0
T33	6780	4	0	0
T34	0	9	0	0
T35	0	7	0	0
T37	0	1	0	0
T38	1783	0	0	0
T39	3559	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	140	0	0
T14	52769	40	0	0
T15	19641	20	0	0
T16	0	20	0	0
T23	0	20	0	0
T24	0	40	0	0
T25	3042	0	0	0
T26	1475	0	0	0
T27	7180	0	0	0
T28	6449	0	0	0
T29	15462	0	0	0
T30	18720	0	0	0
T31	3028	0	0	0
T32	1758	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	3441	0	0
T5	2787	5	0	0
T6	5072	3	0	0
T7	2384	1	0	0
T8	2410	1	0	0
T9	583031	71	0	0
T10	2539	0	0	0
T11	0	1	0	0
T19	47977	0	0	0
T33	6780	4	0	0
T34	0	9	0	0
T35	0	7	0	0
T37	0	1	0	0
T38	1783	0	0	0
T39	3559	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21647678	892043	0	0
T1	3599	28	0	0
T2	1084	10	0	0
T3	18460	780	0	0
T4	1357	0	0	0
T5	2787	168	0	0
T6	5072	1358	0	0
T7	2384	0	0	0
T8	2410	0	0	0
T9	583031	27882	0	0
T10	2539	0	0	0
T19	0	4710	0	0
T20	0	4774	0	0
T33	0	168	0	0
T77	0	5	0	0