Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21751 1 T3 50 T5 2 T7 88
auto[1] 20589 1 T3 48 T5 8 T7 80


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21643 1 T3 44 T5 2 T7 99
auto[1] 20697 1 T3 54 T5 8 T7 69


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20635 1 T3 52 T5 2 T7 88
auto[1] 21705 1 T3 46 T5 8 T7 80


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24104 1 T3 79 T5 5 T7 95
auto[1] 18236 1 T3 19 T5 5 T7 73


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20943 1 T3 52 T5 2 T7 87
auto[1] 21397 1 T3 46 T5 8 T7 81


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21508 1 T3 51 T5 6 T7 104
auto[1] 20832 1 T3 47 T5 4 T7 64


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 708 1 T3 2 T7 4 T8 3
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 518 1 T7 3 T8 3 T9 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 734 1 T3 3 T7 4 T8 4
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 563 1 T3 2 T7 3 T8 4
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 755 1 T3 5 T7 5 T8 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 572 1 T3 1 T7 5 T8 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1226 1 T3 3 T7 7 T9 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1025 1 T3 1 T7 6 T9 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 760 1 T3 2 T7 1 T8 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 576 1 T8 1 T9 1 T28 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 783 1 T3 2 T7 4 T28 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 588 1 T7 2 T28 1 T24 4
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 741 1 T3 1 T7 5 T8 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 554 1 T7 5 T8 1 T28 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 724 1 T3 1 T5 1 T8 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 541 1 T5 1 T8 2 T67 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 781 1 T3 1 T7 3 T8 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 596 1 T3 1 T7 1 T8 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 764 1 T3 4 T7 3 T8 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 590 1 T3 1 T7 2 T8 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 731 1 T3 3 T7 2 T24 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 527 1 T7 1 T24 2 T30 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 687 1 T3 1 T7 3 T8 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 512 1 T7 3 T8 3 T30 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 753 1 T3 3 T7 2 T8 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 570 1 T3 2 T7 2 T8 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 768 1 T3 4 T7 3 T8 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 582 1 T3 1 T7 2 T8 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 757 1 T3 4 T7 1 T8 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 568 1 T3 1 T7 1 T8 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 685 1 T3 1 T7 3 T8 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 512 1 T7 2 T8 1 T28 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 736 1 T3 3 T7 6 T14 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 539 1 T3 1 T7 5 T67 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 770 1 T7 6 T8 2 T24 3
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 580 1 T7 5 T8 2 T24 3
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 696 1 T3 2 T7 2 T8 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 521 1 T7 2 T8 1 T67 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 707 1 T3 2 T7 5 T8 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 516 1 T7 3 T8 2 T9 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 676 1 T3 4 T8 2 T67 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 517 1 T3 1 T8 2 T67 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 766 1 T3 4 T7 1 T8 4
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 586 1 T3 1 T7 1 T8 4
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 795 1 T3 1 T7 3 T9 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 580 1 T7 2 T9 1 T24 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 736 1 T3 2 T7 2 T8 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 554 1 T7 2 T8 1 T67 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 719 1 T3 2 T7 6 T8 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 545 1 T7 5 T8 2 T9 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 721 1 T3 4 T5 1 T7 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 548 1 T3 1 T5 1 T7 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 727 1 T3 3 T5 1 T7 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 559 1 T3 1 T5 1 T24 3
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 759 1 T3 3 T5 1 T8 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 576 1 T3 1 T5 1 T8 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 721 1 T3 2 T7 4 T8 4
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 553 1 T3 1 T7 4 T8 4
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 755 1 T7 1 T28 1 T67 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 577 1 T7 1 T28 1 T67 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 733 1 T3 4 T7 4 T8 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 551 1 T3 1 T7 3 T8 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 730 1 T3 3 T5 1 T7 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 540 1 T3 1 T5 1 T7 1

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