Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	417410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

212671

1

T1

650

T2

437

T3

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	405070	1			T1	1391		T2	900		T3	85
values[0x0]	112176	1			T1	219		T2	214		T3	15
values[0x1]	112835	1			T1	237		T2	238		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	331010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

299071

1

T1

928

T2

651

T3

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2664	1			T4	3		T9	6		T10	4
valid_sources[0x01]	1870	1			T2	9		T9	8		T10	9
valid_sources[0x02]	2562	1			T7	2		T9	4		T10	5
valid_sources[0x03]	1915	1			T9	4		T10	1		T38	9
valid_sources[0x04]	1867	1			T7	4		T8	2		T9	5
valid_sources[0x05]	7727	1			T2	6		T9	4		T38	11
valid_sources[0x06]	1938	1			T2	5		T4	1		T8	5
valid_sources[0x07]	2046	1			T2	14		T8	19		T9	4
valid_sources[0x08]	2277	1			T8	1		T9	2		T10	3
valid_sources[0x09]	2406	1			T4	1		T7	1		T8	3
valid_sources[0x0a]	6095	1			T2	4		T4	12		T8	1
valid_sources[0x0b]	2024	1			T4	2		T9	2		T10	7
valid_sources[0x0c]	3154	1			T2	29		T7	2		T9	6
valid_sources[0x0d]	4588	1			T9	8		T10	9		T38	8
valid_sources[0x0e]	2201	1			T8	4		T9	7		T10	10
valid_sources[0x0f]	2781	1			T2	3		T4	1		T9	4
valid_sources[0x10]	1829	1			T2	10		T9	9		T10	4
valid_sources[0x11]	2061	1			T2	5		T7	1		T9	3
valid_sources[0x12]	1991	1			T2	16		T9	5		T10	10
valid_sources[0x13]	1920	1			T9	4		T38	8		T25	4
valid_sources[0x14]	2414	1			T2	5		T7	2		T8	6
valid_sources[0x15]	2557	1			T2	3		T8	3		T9	7
valid_sources[0x16]	2180	1			T2	1		T8	2		T9	6
valid_sources[0x17]	2373	1			T2	7		T4	1		T9	3
valid_sources[0x18]	2445	1			T2	11		T9	6		T10	2
valid_sources[0x19]	2023	1			T2	7		T4	1		T8	1
valid_sources[0x1a]	1897	1			T2	2		T9	1		T10	8
valid_sources[0x1b]	2881	1			T2	3		T4	4		T9	3
valid_sources[0x1c]	2364	1			T4	7		T8	5		T9	5
valid_sources[0x1d]	2301	1			T2	12		T7	2		T9	1
valid_sources[0x1e]	2281	1			T2	7		T7	1		T9	2
valid_sources[0x1f]	2039	1			T2	7		T4	2		T8	9
valid_sources[0x20]	2094	1			T2	2		T8	2		T9	3
valid_sources[0x21]	1946	1			T2	1		T4	5		T8	2
valid_sources[0x22]	1988	1			T9	7		T10	6		T38	6
valid_sources[0x23]	2289	1			T7	1		T9	3		T10	9
valid_sources[0x24]	1993	1			T2	7		T4	1		T9	4
valid_sources[0x25]	1787	1			T4	3		T8	3		T9	7
valid_sources[0x26]	1826	1			T2	3		T9	3		T10	3
valid_sources[0x27]	1788	1			T2	4		T8	2		T9	7
valid_sources[0x28]	2060	1			T2	2		T7	3		T9	4
valid_sources[0x29]	2177	1			T2	1		T8	1		T9	5
valid_sources[0x2a]	2026	1			T2	1		T4	2		T8	8
valid_sources[0x2b]	2154	1			T2	4		T4	4		T9	6
valid_sources[0x2c]	1922	1			T2	3		T4	2		T8	5
valid_sources[0x2d]	2082	1			T2	11		T7	1		T9	6
valid_sources[0x2e]	2919	1			T2	9		T4	2		T9	4
valid_sources[0x2f]	1865	1			T9	1		T10	5		T38	8
valid_sources[0x30]	2055	1			T2	1		T9	2		T10	6
valid_sources[0x31]	1864	1			T2	5		T7	2		T8	2
valid_sources[0x32]	2230	1			T2	1		T9	3		T38	11
valid_sources[0x33]	3685	1			T2	10		T8	3		T9	6
valid_sources[0x34]	2019	1			T2	4		T8	1		T9	2
valid_sources[0x35]	2016	1			T2	3		T7	5		T8	3
valid_sources[0x36]	1911	1			T2	6		T4	1		T7	5
valid_sources[0x37]	2053	1			T2	2		T8	6		T9	2
valid_sources[0x38]	4440	1			T2	5		T4	3		T7	4
valid_sources[0x39]	3059	1			T2	22		T4	5		T8	2
valid_sources[0x3a]	1913	1			T2	5		T4	4		T8	1
valid_sources[0x3b]	1948	1			T2	3		T7	6		T9	3
valid_sources[0x3c]	6420	1			T2	6		T9	3		T10	2
valid_sources[0x3d]	1937	1			T2	3		T8	2		T9	1
valid_sources[0x3e]	1746	1			T2	14		T4	4		T7	1
valid_sources[0x3f]	2075	1			T2	1		T7	1		T9	4
valid_sources[0x40]	2452	1			T2	4		T8	2		T9	5
valid_sources[0x41]	2173	1			T8	2		T9	3		T10	2
valid_sources[0x42]	4511	1			T2	14		T9	3		T10	16
valid_sources[0x43]	2878	1			T2	20		T4	6		T8	1
valid_sources[0x44]	2006	1			T2	7		T8	1		T9	3
valid_sources[0x45]	1925	1			T9	3		T10	3		T38	10
valid_sources[0x46]	1822	1			T2	1		T10	2		T38	7
valid_sources[0x47]	1814	1			T2	3		T8	4		T9	4
valid_sources[0x48]	2222	1			T2	17		T9	4		T10	8
valid_sources[0x49]	3078	1			T2	10		T7	1		T9	3
valid_sources[0x4a]	2008	1			T2	10		T9	3		T10	4
valid_sources[0x4b]	1925	1			T4	7		T8	2		T9	1
valid_sources[0x4c]	2519	1			T2	3		T7	6		T9	2
valid_sources[0x4d]	1993	1			T2	2		T4	2		T8	1
valid_sources[0x4e]	6304	1			T2	2		T7	2		T8	1
valid_sources[0x4f]	1882	1			T2	1		T7	1		T9	5
valid_sources[0x50]	6094	1			T2	5		T4	7		T9	6
valid_sources[0x51]	2073	1			T4	1		T9	4		T38	9
valid_sources[0x52]	4093	1			T2	15		T8	2		T9	5
valid_sources[0x53]	2180	1			T2	1		T4	2		T6	1
valid_sources[0x54]	1896	1			T2	2		T7	1		T8	4
valid_sources[0x55]	2093	1			T2	8		T8	4		T9	5
valid_sources[0x56]	1824	1			T2	4		T8	2		T9	2
valid_sources[0x57]	2221	1			T2	9		T4	1		T8	3
valid_sources[0x58]	1914	1			T2	2		T7	1		T8	6
valid_sources[0x59]	1732	1			T2	7		T4	5		T8	7
valid_sources[0x5a]	1885	1			T2	11		T8	2		T9	7
valid_sources[0x5b]	1908	1			T2	3		T9	3		T10	1
valid_sources[0x5c]	2066	1			T2	7		T7	2		T8	1
valid_sources[0x5d]	2458	1			T2	4		T4	7		T8	1
valid_sources[0x5e]	4684	1			T2	8		T4	3		T8	1
valid_sources[0x5f]	2259	1			T2	3		T7	4		T8	2
valid_sources[0x60]	1831	1			T9	7		T10	1		T38	3
valid_sources[0x61]	1976	1			T2	37		T9	4		T10	1
valid_sources[0x62]	2864	1			T7	1		T9	7		T10	1
valid_sources[0x63]	2180	1			T2	1		T4	1		T9	5
valid_sources[0x64]	2003	1			T2	3		T7	1		T9	3
valid_sources[0x65]	2103	1			T7	1		T9	7		T10	9
valid_sources[0x66]	2013	1			T2	7		T7	2		T9	4
valid_sources[0x67]	1887	1			T4	5		T7	2		T8	9
valid_sources[0x68]	1991	1			T2	7		T8	2		T9	6
valid_sources[0x69]	1919	1			T2	8		T9	8		T10	11
valid_sources[0x6a]	3351	1			T2	8		T7	1		T9	2
valid_sources[0x6b]	2575	1			T2	8		T7	6		T9	4
valid_sources[0x6c]	1885	1			T2	3		T9	1		T10	2
valid_sources[0x6d]	2007	1			T2	3		T8	5		T9	6
valid_sources[0x6e]	1931	1			T2	1		T8	4		T9	5
valid_sources[0x6f]	2031	1			T2	17		T8	1		T9	2
valid_sources[0x70]	1929	1			T4	1		T7	1		T9	3
valid_sources[0x71]	1963	1			T8	2		T9	6		T10	5
valid_sources[0x72]	2953	1			T2	9		T8	6		T9	5
valid_sources[0x73]	2124	1			T4	1		T8	2		T9	2
valid_sources[0x74]	2164	1			T2	4		T7	1		T9	5
valid_sources[0x75]	1794	1			T2	12		T9	4		T10	5
valid_sources[0x76]	2108	1			T9	3		T10	5		T38	11
valid_sources[0x77]	2852	1			T2	5		T9	1		T10	12
valid_sources[0x78]	1906	1			T2	1		T9	2		T10	5
valid_sources[0x79]	2299	1			T2	6		T8	2		T9	4
valid_sources[0x7a]	2034	1			T2	7		T4	1		T9	6
valid_sources[0x7b]	2093	1			T2	1		T9	3		T10	2
valid_sources[0x7c]	2210	1			T2	16		T5	1		T8	2
valid_sources[0x7d]	4044	1			T2	4		T8	4		T9	5
valid_sources[0x7e]	2426	1			T2	11		T4	5		T9	6
valid_sources[0x7f]	1871	1			T2	7		T9	5		T10	5
valid_sources[0x80]	11123	1			T2	5		T4	15		T9	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

145358

1

T1

538

T2

314

T3

43

values[0x0]

all_enables

biggest_size

43239

1

T1

78

T2

82

T3

5

values[0x1]

all_enables

biggest_size

24074

1

T1

34

T2

41

T3

2