SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34552 | 1 | T2 | 420 | T10 | 412 | T38 | 389 | ||||
others[1] | 34597 | 1 | T2 | 401 | T10 | 401 | T38 | 406 | ||||
others[2] | 34607 | 1 | T2 | 371 | T10 | 410 | T38 | 408 | ||||
others[3] | 58307 | 1 | T2 | 670 | T10 | 654 | T38 | 675 | ||||
false | 13095 | 1 | T1 | 32 | T2 | 50 | T8 | 22 | ||||
true | 20989 | 1 | T1 | 39 | T2 | 101 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34715 | 1 | T2 | 400 | T10 | 416 | T38 | 416 | ||||
others[1] | 34692 | 1 | T2 | 387 | T10 | 388 | T38 | 376 | ||||
others[2] | 34752 | 1 | T2 | 416 | T10 | 404 | T38 | 377 | ||||
others[3] | 57947 | 1 | T2 | 662 | T10 | 667 | T24 | 1 | ||||
false | 9102 | 1 | T1 | 16 | T2 | 50 | T8 | 11 | ||||
true | 17060 | 1 | T1 | 23 | T2 | 101 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 526 | 1 | T1 | 2 | T3 | 1 | T12 | 1 | ||||
others[1] | 541 | 1 | T1 | 1 | T3 | 3 | T12 | 1 | ||||
others[2] | 536 | 1 | T7 | 1 | T12 | 1 | T40 | 1 | ||||
others[3] | 849 | 1 | T1 | 1 | T7 | 2 | T24 | 1 | ||||
false | 9252 | 1 | T1 | 20 | T2 | 1 | T3 | 21 | ||||
true | 2542 | 1 | T1 | 9 | T3 | 4 | T7 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |