Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17773798	16597	0	0
intr_enable_rd_A	17773798	25756	0	0
reset_en_rd_A	17773798	1761	0	0
reset_en_regwen_rd_A	17773798	1541	0	0
wake_info_capture_dis_rd_A	17773798	1450	0	0
wakeup_en_rd_A	17773798	2649	0	0
wakeup_en_regwen_rd_A	17773798	1481	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17773798	16597	0	0
T20	499715	143	0	0
T21	0	7	0	0
T22	0	9	0	0
T48	2898	0	0	0
T49	0	7	0	0
T50	0	912	0	0
T51	0	669	0	0
T52	0	51	0	0
T53	0	113	0	0
T57	0	109	0	0
T59	5290	0	0	0
T122	0	52	0	0
T123	5225	0	0	0
T124	1750	0	0	0
T125	3000	0	0	0
T126	17474	0	0	0
T127	6474	0	0	0
T128	3853	0	0	0
T129	6218	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17773798	25756	0	0
T4	6547	37	0	0
T5	1230	0	0	0
T6	2386	0	0	0
T7	3713	39	0	0
T8	11177	0	0	0
T9	19293	0	0	0
T10	57446	0	0	0
T11	797	0	0	0
T37	30653	260	0	0
T41	0	70	0	0
T42	0	24	0	0
T71	1131	0	0	0
T123	0	10	0	0
T126	0	25	0	0
T130	0	4	0	0
T131	0	50	0	0
T132	0	8	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17773798	1761	0	0
T49	11764	111	0	0
T55	5943	0	0	0
T56	3932	0	0	0
T60	3733	6	0	0
T62	9642	2	0	0
T63	10388	16	0	0
T69	0	126	0	0
T74	3673	0	0	0
T81	2034	60	0	0
T86	0	12	0	0
T87	0	2	0	0
T89	0	195	0	0
T92	0	34	0	0
T133	1420	0	0	0
T134	665	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17773798	1541	0	0
T49	11764	82	0	0
T55	5943	0	0	0
T56	3932	0	0	0
T60	3733	1	0	0
T62	9642	3	0	0
T63	10388	19	0	0
T69	0	67	0	0
T74	3673	0	0	0
T81	2034	18	0	0
T86	0	40	0	0
T87	0	2	0	0
T89	0	220	0	0
T92	0	38	0	0
T133	1420	0	0	0
T134	665	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17773798	1450	0	0
T49	11764	56	0	0
T55	5943	0	0	0
T56	3932	0	0	0
T60	3733	21	0	0
T62	9642	16	0	0
T63	10388	9	0	0
T69	0	58	0	0
T74	3673	0	0	0
T81	2034	39	0	0
T86	0	14	0	0
T87	0	1	0	0
T89	0	239	0	0
T92	0	54	0	0
T133	1420	0	0	0
T134	665	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17773798	2649	0	0
T49	11764	326	0	0
T55	5943	0	0	0
T56	3932	0	0	0
T60	3733	56	0	0
T62	9642	24	0	0
T63	10388	25	0	0
T69	0	240	0	0
T74	3673	0	0	0
T81	2034	13	0	0
T86	0	4	0	0
T87	0	19	0	0
T89	0	199	0	0
T92	0	117	0	0
T133	1420	0	0	0
T134	665	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17773798	1481	0	0
T49	11764	79	0	0
T55	5943	0	0	0
T56	3932	0	0	0
T60	3733	29	0	0
T62	9642	1	0	0
T63	10388	8	0	0
T69	0	62	0	0
T74	3673	0	0	0
T81	2034	11	0	0
T86	0	25	0	0
T89	0	256	0	0
T92	0	30	0	0
T133	1420	0	0	0
T134	665	0	0	0
T135	0	263	0	0