Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	17161594	35670	0	0
IoStatusRise_A	17161594	39675	0	0
MainStatusFall_A	17161594	35671	0	0
MainStatusRise_A	17161594	39676	0	0
UsbStatusFall_A	17161594	26886	0	0
UsbStatusRise_A	17161594	30241	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	35670	0	0
T1	31210	83	0	0
T2	21980	83	0	0
T3	7823	18	0	0
T4	6547	13	0	0
T5	1230	1	0	0
T6	2386	1	0	0
T7	3713	15	0	0
T8	11177	17	0	0
T9	19293	90	0	0
T10	57446	89	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	39675	0	0
T1	31210	90	0	0
T2	21980	84	0	0
T3	7823	20	0	0
T4	6547	14	0	0
T5	1230	3	0	0
T6	2386	3	0	0
T7	3713	16	0	0
T8	11177	18	0	0
T9	19293	98	0	0
T10	57446	90	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	35671	0	0
T1	31210	83	0	0
T2	21980	83	0	0
T3	7823	18	0	0
T4	6547	13	0	0
T5	1230	1	0	0
T6	2386	1	0	0
T7	3713	15	0	0
T8	11177	17	0	0
T9	19293	90	0	0
T10	57446	89	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	39676	0	0
T1	31210	90	0	0
T2	21980	84	0	0
T3	7823	20	0	0
T4	6547	14	0	0
T5	1230	3	0	0
T6	2386	3	0	0
T7	3713	16	0	0
T8	11177	18	0	0
T9	19293	98	0	0
T10	57446	90	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	26886	0	0
T1	31210	56	0	0
T2	21980	49	0	0
T3	7823	18	0	0
T4	6547	11	0	0
T5	1230	1	0	0
T6	2386	1	0	0
T7	3713	15	0	0
T8	11177	11	0	0
T9	19293	65	0	0
T10	57446	48	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	30241	0	0
T1	31210	63	0	0
T2	21980	49	0	0
T3	7823	20	0	0
T4	6547	11	0	0
T5	1230	3	0	0
T6	2386	3	0	0
T7	3713	16	0	0
T8	11177	12	0	0
T9	19293	70	0	0
T10	57446	49	0	0