Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	17161594	39282	0	0
RomAllowCheckGoodState_A	17161594	39332	0	0
RomBlockActiveState_A	17161594	38089	0	0
RomBlockCheckGoodState_A	17161594	354192	0	0
RomIntgChkDisFalse_A	17161594	16671528	0	0
RomIntgChkDisTrue_A	17161594	123718	0	0
RstreqChkEsctimeout_A	17161594	2768	0	0
RstreqChkFsmterm_A	17161594	140	0	0
RstreqChkGlbesc_A	17161594	2768	0	0
RstreqChkMainpd_A	17161594	744173	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	39282	0	0
T1	31210	90	0	0
T2	21980	84	0	0
T3	7823	13	0	0
T4	6547	14	0	0
T5	1230	3	0	0
T6	2386	3	0	0
T7	3713	16	0	0
T8	11177	18	0	0
T9	19293	98	0	0
T10	57446	90	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	39332	0	0
T1	31210	90	0	0
T2	21980	84	0	0
T3	7823	14	0	0
T4	6547	14	0	0
T5	1230	3	0	0
T6	2386	3	0	0
T7	3713	16	0	0
T8	11177	18	0	0
T9	19293	98	0	0
T10	57446	90	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	38089	0	0
T2	21980	1	0	0
T3	7823	0	0	0
T4	6547	0	0	0
T5	1230	0	0	0
T6	2386	0	0	0
T7	3713	0	0	0
T8	11177	0	0	0
T9	19293	0	0	0
T10	57446	0	0	0
T24	0	542	0	0
T37	30653	0	0	0
T78	0	4	0	0
T127	0	1391	0	0
T129	0	1245	0	0
T136	0	26	0	0
T137	0	21	0	0
T138	0	1527	0	0
T139	0	599	0	0
T140	0	706	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	354192	0	0
T1	31210	367	0	0
T2	21980	1529	0	0
T3	7823	0	0	0
T4	6547	0	0	0
T5	1230	0	0	0
T6	2386	0	0	0
T7	3713	0	0	0
T8	11177	252	0	0
T9	19293	389	0	0
T10	57446	4027	0	0
T13	0	460	0	0
T24	0	338	0	0
T25	0	1295	0	0
T37	0	480	0	0
T38	0	4116	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	16671528	0	0
T1	31210	30699	0	0
T2	21980	21899	0	0
T3	7823	6948	0	0
T4	6547	6477	0	0
T5	1230	1062	0	0
T6	2386	2236	0	0
T7	3713	3660	0	0
T8	11177	11103	0	0
T9	19293	18654	0	0
T10	57446	57357	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	123718	0	0
T12	12344	0	0	0
T24	3353	192	0	0
T25	17673	551	0	0
T26	51412	1800	0	0
T38	59859	0	0	0
T40	5961	0	0	0
T58	11808	0	0	0
T127	6474	346	0	0
T129	0	429	0	0
T137	0	259	0	0
T138	0	1762	0	0
T139	0	52	0	0
T140	0	929	0	0
T141	0	2646	0	0
T142	2060	0	0	0
T143	44201	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	2768	0	0
T1	31210	12	0	0
T2	21980	0	0	0
T3	7823	7	0	0
T4	6547	0	0	0
T5	1230	1	0	0
T6	2386	1	0	0
T7	3713	5	0	0
T8	11177	0	0	0
T9	19293	0	0	0
T10	57446	0	0	0
T11	0	1	0	0
T12	0	9	0	0
T24	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	140	0	0
T17	24556	20	0	0
T18	8845	20	0	0
T19	0	40	0	0
T27	0	20	0	0
T28	0	40	0	0
T29	1779	0	0	0
T30	3699	0	0	0
T31	58400	0	0	0
T32	2470	0	0	0
T33	1458	0	0	0
T34	2560	0	0	0
T35	2383	0	0	0
T36	169456	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	2768	0	0
T1	31210	12	0	0
T2	21980	0	0	0
T3	7823	7	0	0
T4	6547	0	0	0
T5	1230	1	0	0
T6	2386	1	0	0
T7	3713	5	0	0
T8	11177	0	0	0
T9	19293	0	0	0
T10	57446	0	0	0
T11	0	1	0	0
T12	0	9	0	0
T24	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17161594	744173	0	0
T1	31210	1527	0	0
T2	21980	1656	0	0
T3	7823	237	0	0
T4	6547	0	0	0
T5	1230	0	0	0
T6	2386	0	0	0
T7	3713	145	0	0
T8	11177	0	0	0
T9	19293	548	0	0
T10	57446	4196	0	0
T12	0	782	0	0
T24	0	556	0	0
T37	0	400	0	0
T38	0	8927	0	0