Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	473980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246437

1

T1

32

T2

29

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	471682	1			T1	182		T2	52		T3	182
values[0x0]	123944	1			T1	28		T2	9		T3	30
values[0x1]	124791	1			T1	34		T2	7		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	375533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

344884

1

T1

89

T2

33

T3

79

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2150	1			T4	1		T5	6		T8	4
valid_sources[0x01]	2107	1			T4	6		T5	4		T8	6
valid_sources[0x02]	1933	1			T4	5		T5	7		T8	4
valid_sources[0x03]	2208	1			T4	3		T5	1		T7	18
valid_sources[0x04]	1920	1			T4	3		T5	4		T8	4
valid_sources[0x05]	2176	1			T4	3		T5	2		T8	3
valid_sources[0x06]	2312	1			T4	1		T5	3		T8	4
valid_sources[0x07]	2522	1			T1	7		T4	1		T5	4
valid_sources[0x08]	2364	1			T1	6		T4	2		T5	6
valid_sources[0x09]	8011	1			T5	2		T6	5		T8	3
valid_sources[0x0a]	2211	1			T4	2		T5	5		T8	3
valid_sources[0x0b]	2321	1			T1	2		T4	2		T5	2
valid_sources[0x0c]	1985	1			T5	4		T8	2		T28	5
valid_sources[0x0d]	2347	1			T4	4		T5	5		T8	2
valid_sources[0x0e]	1988	1			T4	1		T5	2		T8	2
valid_sources[0x0f]	2104	1			T4	5		T5	6		T8	4
valid_sources[0x10]	1943	1			T4	2		T5	2		T6	2
valid_sources[0x11]	6572	1			T4	2		T5	3		T8	5
valid_sources[0x12]	2220	1			T4	1		T5	4		T8	4
valid_sources[0x13]	1929	1			T1	1		T4	4		T5	2
valid_sources[0x14]	2375	1			T4	1		T5	6		T8	4
valid_sources[0x15]	2082	1			T4	2		T5	4		T8	3
valid_sources[0x16]	2094	1			T1	4		T4	1		T5	3
valid_sources[0x17]	2054	1			T4	2		T5	2		T8	7
valid_sources[0x18]	2170	1			T4	2		T5	1		T7	3
valid_sources[0x19]	8072	1			T4	6		T5	5		T8	2
valid_sources[0x1a]	1975	1			T4	2		T5	3		T8	3
valid_sources[0x1b]	2575	1			T5	3		T8	1		T14	2
valid_sources[0x1c]	5484	1			T4	1		T5	4		T8	8
valid_sources[0x1d]	1971	1			T4	1		T5	7		T8	8
valid_sources[0x1e]	1940	1			T4	2		T5	2		T8	3
valid_sources[0x1f]	2099	1			T3	18		T5	1		T8	8
valid_sources[0x20]	2235	1			T1	17		T5	2		T8	5
valid_sources[0x21]	2060	1			T28	8		T72	5		T118	3
valid_sources[0x22]	4650	1			T4	3		T5	6		T8	5
valid_sources[0x23]	2247	1			T1	7		T4	3		T5	7
valid_sources[0x24]	2030	1			T4	2		T5	1		T8	5
valid_sources[0x25]	2158	1			T1	6		T5	3		T8	4
valid_sources[0x26]	2203	1			T4	1		T5	2		T8	1
valid_sources[0x27]	1990	1			T5	3		T8	5		T11	1
valid_sources[0x28]	1867	1			T4	4		T5	4		T8	2
valid_sources[0x29]	2377	1			T4	1		T5	5		T6	1
valid_sources[0x2a]	5185	1			T4	3		T5	8		T6	1
valid_sources[0x2b]	2130	1			T4	2		T5	5		T8	8
valid_sources[0x2c]	3386	1			T4	2		T5	10		T8	5
valid_sources[0x2d]	5145	1			T4	1		T5	5		T7	11
valid_sources[0x2e]	4519	1			T4	3		T5	4		T8	4
valid_sources[0x2f]	2115	1			T1	1		T4	1		T5	4
valid_sources[0x30]	2008	1			T4	2		T5	4		T8	1
valid_sources[0x31]	2248	1			T4	2		T5	5		T8	5
valid_sources[0x32]	1967	1			T4	1		T5	1		T8	4
valid_sources[0x33]	2825	1			T4	2		T5	5		T8	6
valid_sources[0x34]	3377	1			T4	5		T5	1		T8	6
valid_sources[0x35]	2228	1			T1	2		T4	2		T5	2
valid_sources[0x36]	2141	1			T4	1		T5	2		T8	3
valid_sources[0x37]	4643	1			T4	1		T5	3		T8	3
valid_sources[0x38]	3409	1			T5	9		T8	6		T28	16
valid_sources[0x39]	2099	1			T1	4		T4	1		T5	5
valid_sources[0x3a]	2500	1			T5	2		T8	2		T28	11
valid_sources[0x3b]	4650	1			T4	1		T5	2		T8	1
valid_sources[0x3c]	1999	1			T2	25		T4	3		T5	5
valid_sources[0x3d]	2056	1			T1	3		T4	2		T5	4
valid_sources[0x3e]	2242	1			T4	3		T5	5		T8	1
valid_sources[0x3f]	2059	1			T4	1		T5	8		T8	2
valid_sources[0x40]	2014	1			T4	1		T5	3		T8	4
valid_sources[0x41]	2108	1			T4	1		T5	3		T8	3
valid_sources[0x42]	1992	1			T1	6		T3	7		T4	4
valid_sources[0x43]	2106	1			T4	1		T5	7		T7	17
valid_sources[0x44]	2472	1			T4	3		T5	6		T8	5
valid_sources[0x45]	2078	1			T1	1		T4	3		T5	7
valid_sources[0x46]	2309	1			T4	4		T5	5		T8	2
valid_sources[0x47]	2038	1			T4	3		T5	3		T8	4
valid_sources[0x48]	2862	1			T1	3		T4	3		T5	2
valid_sources[0x49]	2039	1			T4	3		T5	3		T8	1
valid_sources[0x4a]	3413	1			T4	1		T5	2		T8	7
valid_sources[0x4b]	2325	1			T4	2		T5	1		T8	4
valid_sources[0x4c]	5962	1			T4	2		T5	4		T8	3
valid_sources[0x4d]	2125	1			T4	3		T5	4		T8	3
valid_sources[0x4e]	2601	1			T5	4		T8	5		T28	1
valid_sources[0x4f]	2054	1			T5	3		T7	4		T8	5
valid_sources[0x50]	2310	1			T4	1		T5	2		T7	7
valid_sources[0x51]	2147	1			T1	3		T4	1		T5	6
valid_sources[0x52]	2533	1			T4	1		T8	7		T28	8
valid_sources[0x53]	2145	1			T4	1		T5	3		T8	2
valid_sources[0x54]	2060	1			T5	3		T8	4		T15	5
valid_sources[0x55]	2031	1			T5	3		T8	5		T14	3
valid_sources[0x56]	2236	1			T1	1		T4	2		T8	5
valid_sources[0x57]	2137	1			T1	2		T4	3		T5	1
valid_sources[0x58]	2335	1			T1	1		T4	1		T5	5
valid_sources[0x59]	3412	1			T4	2		T5	1		T6	1
valid_sources[0x5a]	2353	1			T3	54		T4	1		T8	4
valid_sources[0x5b]	2238	1			T4	4		T5	4		T8	2
valid_sources[0x5c]	1987	1			T4	3		T5	3		T8	5
valid_sources[0x5d]	2147	1			T4	4		T5	6		T8	4
valid_sources[0x5e]	4580	1			T4	3		T5	1		T8	5
valid_sources[0x5f]	1949	1			T1	4		T4	2		T5	4
valid_sources[0x60]	2073	1			T5	3		T8	4		T28	13
valid_sources[0x61]	2047	1			T1	1		T4	1		T5	2
valid_sources[0x62]	2196	1			T1	3		T5	7		T8	2
valid_sources[0x63]	2283	1			T4	4		T5	3		T8	4
valid_sources[0x64]	3071	1			T4	2		T5	5		T8	6
valid_sources[0x65]	2551	1			T4	3		T5	4		T8	6
valid_sources[0x66]	3839	1			T4	3		T5	5		T8	7
valid_sources[0x67]	5994	1			T5	4		T28	6		T15	2
valid_sources[0x68]	2106	1			T4	2		T5	4		T8	4
valid_sources[0x69]	2547	1			T4	2		T5	3		T8	3
valid_sources[0x6a]	2800	1			T1	3		T4	3		T5	1
valid_sources[0x6b]	1970	1			T1	2		T4	1		T5	2
valid_sources[0x6c]	2043	1			T1	1		T4	4		T5	2
valid_sources[0x6d]	2260	1			T4	2		T5	8		T7	13
valid_sources[0x6e]	2132	1			T4	1		T5	4		T8	7
valid_sources[0x6f]	1930	1			T1	3		T5	5		T8	5
valid_sources[0x70]	2313	1			T5	4		T8	4		T28	6
valid_sources[0x71]	2016	1			T5	6		T8	6		T9	5
valid_sources[0x72]	2232	1			T4	3		T5	3		T8	4
valid_sources[0x73]	1930	1			T1	1		T8	5		T28	9
valid_sources[0x74]	2435	1			T2	14		T4	4		T5	5
valid_sources[0x75]	2076	1			T1	4		T4	3		T5	5
valid_sources[0x76]	2008	1			T1	3		T5	4		T8	4
valid_sources[0x77]	3215	1			T5	5		T8	5		T14	2
valid_sources[0x78]	13127	1			T4	1		T5	4		T8	4
valid_sources[0x79]	2561	1			T1	1		T5	5		T8	6
valid_sources[0x7a]	2178	1			T1	1		T4	2		T5	2
valid_sources[0x7b]	2112	1			T1	1		T4	2		T5	2
valid_sources[0x7c]	2324	1			T1	4		T4	1		T5	6
valid_sources[0x7d]	2005	1			T5	4		T8	1		T28	3
valid_sources[0x7e]	1918	1			T1	3		T4	3		T5	2
valid_sources[0x7f]	3213	1			T1	4		T5	2		T7	4
valid_sources[0x80]	2545	1			T3	6		T4	1		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

171893

1

T1

17

T2

25

T3

14

values[0x0]

all_enables

biggest_size

47677

1

T1

11

T2

2

T3

10

values[0x1]

all_enables

biggest_size

26867

1

T1

4

T2

2

T3

4