SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35049 | 1 | T5 | 316 | T8 | 397 | T28 | 386 | ||||
others[1] | 34624 | 1 | T5 | 280 | T8 | 414 | T28 | 401 | ||||
others[2] | 34659 | 1 | T5 | 304 | T8 | 375 | T28 | 401 | ||||
others[3] | 57832 | 1 | T5 | 492 | T8 | 672 | T28 | 684 | ||||
false | 14815 | 1 | T5 | 50 | T8 | 50 | T28 | 50 | ||||
true | 23208 | 1 | T1 | 1 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34541 | 1 | T5 | 312 | T8 | 379 | T28 | 381 | ||||
others[1] | 34799 | 1 | T5 | 319 | T8 | 408 | T28 | 420 | ||||
others[2] | 34912 | 1 | T5 | 290 | T8 | 419 | T28 | 419 | ||||
others[3] | 57681 | 1 | T5 | 481 | T8 | 664 | T28 | 651 | ||||
false | 9976 | 1 | T5 | 50 | T8 | 50 | T28 | 50 | ||||
true | 18418 | 1 | T1 | 1 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 573 | 1 | T1 | 5 | T3 | 6 | T14 | 1 | ||||
others[1] | 564 | 1 | T1 | 8 | T3 | 6 | T16 | 1 | ||||
others[2] | 643 | 1 | T1 | 6 | T3 | 5 | T14 | 2 | ||||
others[3] | 1000 | 1 | T1 | 6 | T3 | 3 | T13 | 2 | ||||
false | 10559 | 1 | T1 | 4 | T2 | 5 | T3 | 7 | ||||
true | 3066 | 1 | T1 | 1 | T3 | 5 | T13 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |