Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17817989	15416	0	0
intr_enable_rd_A	17817989	11581	0	0
reset_en_rd_A	17817989	1172	0	0
reset_en_regwen_rd_A	17817989	1087	0	0
wake_info_capture_dis_rd_A	17817989	986	0	0
wakeup_en_rd_A	17817989	2074	0	0
wakeup_en_regwen_rd_A	17817989	1045	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17817989	15416	0	0
T23	3274	30	0	0
T24	12406	6	0	0
T25	3049	82	0	0
T50	0	35	0	0
T51	0	4	0	0
T52	0	585	0	0
T53	0	508	0	0
T55	0	11	0	0
T60	13690	0	0	0
T63	1850	0	0	0
T64	997	0	0	0
T77	0	15	0	0
T78	810	0	0	0
T79	2628	0	0	0
T80	1884	0	0	0
T81	1467	0	0	0
T98	0	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17817989	11581	0	0
T7	2960	12	0	0
T8	54451	138	0	0
T9	8325	0	0	0
T10	15091	0	0	0
T11	15289	0	0	0
T13	5142	0	0	0
T14	2933	0	0	0
T15	23713	0	0	0
T26	1213	0	0	0
T27	0	206	0	0
T28	58784	0	0	0
T49	0	174	0	0
T103	0	4	0	0
T104	0	60	0	0
T105	0	159	0	0
T106	0	52	0	0
T107	0	52	0	0
T108	0	53	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17817989	1172	0	0
T25	3049	0	0	0
T55	0	108	0	0
T59	4386	102	0	0
T60	13690	144	0	0
T63	1850	0	0	0
T64	997	0	0	0
T65	1586	0	0	0
T78	810	0	0	0
T79	2628	0	0	0
T80	1884	8	0	0
T81	1467	3	0	0
T87	0	10	0	0
T88	0	1	0	0
T90	0	46	0	0
T91	0	7	0	0
T109	0	39	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17817989	1087	0	0
T25	3049	0	0	0
T55	0	71	0	0
T59	4386	128	0	0
T60	13690	163	0	0
T61	0	10	0	0
T63	1850	0	0	0
T64	997	0	0	0
T65	1586	0	0	0
T78	810	0	0	0
T79	2628	0	0	0
T80	1884	4	0	0
T81	1467	3	0	0
T87	0	5	0	0
T88	0	8	0	0
T90	0	62	0	0
T109	0	16	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17817989	986	0	0
T25	3049	0	0	0
T55	0	79	0	0
T59	4386	97	0	0
T60	13690	162	0	0
T63	1850	0	0	0
T64	997	0	0	0
T65	1586	0	0	0
T70	0	35	0	0
T78	810	0	0	0
T79	2628	0	0	0
T80	1884	0	0	0
T81	1467	0	0	0
T87	0	11	0	0
T88	0	15	0	0
T90	0	69	0	0
T91	0	1	0	0
T109	0	17	0	0
T110	0	12	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17817989	2074	0	0
T25	3049	0	0	0
T55	0	284	0	0
T59	4386	96	0	0
T60	13690	138	0	0
T63	1850	0	0	0
T64	997	0	0	0
T65	1586	0	0	0
T78	810	0	0	0
T79	2628	0	0	0
T80	1884	14	0	0
T81	1467	2	0	0
T87	0	23	0	0
T88	0	5	0	0
T90	0	62	0	0
T91	0	11	0	0
T109	0	10	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17817989	1045	0	0
T25	3049	0	0	0
T55	0	70	0	0
T59	4386	111	0	0
T60	13690	143	0	0
T61	0	11	0	0
T63	1850	0	0	0
T64	997	0	0	0
T65	1586	0	0	0
T70	0	35	0	0
T78	810	0	0	0
T79	2628	0	0	0
T80	1884	0	0	0
T81	1467	0	0	0
T87	0	6	0	0
T90	0	68	0	0
T109	0	16	0	0
T110	0	23	0	0
T111	0	26	0	0