Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	17281728	43929	0	0
RomAllowCheckGoodState_A	17281728	43980	0	0
RomBlockActiveState_A	17281728	28656	0	0
RomBlockCheckGoodState_A	17281728	396020	0	0
RomIntgChkDisFalse_A	17281728	16743992	0	0
RomIntgChkDisTrue_A	17281728	131606	0	0
RstreqChkEsctimeout_A	17281728	3357	0	0
RstreqChkFsmterm_A	17281728	160	0	0
RstreqChkGlbesc_A	17281728	3361	0	0
RstreqChkMainpd_A	17281728	753004	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	43929	0	0
T1	5090	2	0	0
T2	3195	5	0	0
T3	3691	6	0	0
T4	12711	14	0	0
T5	13707	83	0	0
T6	2058	10	0	0
T7	2960	8	0	0
T8	54451	89	0	0
T9	8325	9	0	0
T10	15091	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	43980	0	0
T1	5090	2	0	0
T2	3195	5	0	0
T3	3691	6	0	0
T4	12711	14	0	0
T5	13707	83	0	0
T6	2058	10	0	0
T7	2960	8	0	0
T8	54451	89	0	0
T9	8325	9	0	0
T10	15091	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	28656	0	0
T20	8665	0	0	0
T26	1213	3	0	0
T27	37115	0	0	0
T39	3085	0	0	0
T40	7674	0	0	0
T42	1274	0	0	0
T43	0	1541	0	0
T49	26481	14	0	0
T72	56687	0	0	0
T73	4730	0	0	0
T103	1799	0	0	0
T105	0	13	0	0
T112	0	3	0	0
T113	0	172	0	0
T114	0	302	0	0
T115	0	640	0	0
T116	0	156	0	0
T117	0	94	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	396020	0	0
T5	13707	580	0	0
T6	2058	0	0	0
T7	2960	0	0	0
T8	54451	3338	0	0
T9	8325	0	0	0
T10	15091	0	0	0
T11	15289	0	0	0
T13	5142	0	0	0
T14	2933	0	0	0
T15	0	505	0	0
T16	0	321	0	0
T27	0	2268	0	0
T28	58784	4103	0	0
T43	0	1080	0	0
T49	0	1277	0	0
T72	0	4082	0	0
T118	0	437	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	16743992	0	0
T1	5090	5037	0	0
T2	3195	2857	0	0
T3	3691	3594	0	0
T4	12711	12637	0	0
T5	13707	13442	0	0
T6	2058	1993	0	0
T7	2960	2868	0	0
T8	54451	54323	0	0
T9	8325	8227	0	0
T10	15091	15009	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	131606	0	0
T5	13707	172	0	0
T6	2058	0	0	0
T7	2960	0	0	0
T8	54451	0	0	0
T9	8325	0	0	0
T10	15091	0	0	0
T11	15289	0	0	0
T13	5142	0	0	0
T14	2933	0	0	0
T26	0	65	0	0
T27	0	891	0	0
T28	58784	0	0	0
T43	0	525	0	0
T72	0	1449	0	0
T105	0	311	0	0
T119	0	318	0	0
T120	0	227	0	0
T121	0	1812	0	0
T122	0	2274	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	3357	0	0
T10	15091	1	0	0
T11	15289	1	0	0
T13	5142	3	0	0
T14	2933	5	0	0
T15	23713	11	0	0
T16	0	6	0	0
T20	0	10	0	0
T26	1213	2	0	0
T27	37115	0	0	0
T28	58784	0	0	0
T39	3085	6	0	0
T40	0	7	0	0
T42	1274	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	160	0	0
T20	8665	20	0	0
T21	24736	40	0	0
T22	0	20	0	0
T29	0	40	0	0
T30	0	40	0	0
T31	3405	0	0	0
T32	3456	0	0	0
T33	773	0	0	0
T34	4658	0	0	0
T35	2978	0	0	0
T36	1370	0	0	0
T37	4570	0	0	0
T38	20186	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	3361	0	0
T10	15091	1	0	0
T11	15289	1	0	0
T13	5142	3	0	0
T14	2933	5	0	0
T15	23713	11	0	0
T16	0	6	0	0
T20	0	10	0	0
T26	1213	2	0	0
T27	37115	0	0	0
T28	58784	0	0	0
T39	3085	6	0	0
T40	0	7	0	0
T42	1274	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17281728	753004	0	0
T5	13707	921	0	0
T6	2058	0	0	0
T7	2960	0	0	0
T8	54451	4422	0	0
T9	8325	0	0	0
T10	15091	0	0	0
T11	15289	0	0	0
T13	5142	772	0	0
T14	2933	154	0	0
T15	0	581	0	0
T16	0	650	0	0
T26	0	51	0	0
T27	0	2975	0	0
T28	58784	5770	0	0
T39	0	104	0	0