Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	421680	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

219251

1

T1

8

T2

27

T3

78

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	410921	1			T1	20		T2	182		T3	170
values[0x0]	114404	1			T1	4		T2	32		T3	13
values[0x1]	115606	1			T1	6		T2	30		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	333557	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

307374

1

T1

12

T2

94

T3

99

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1821	1			T3	1		T4	1		T29	5
valid_sources[0x01]	2354	1			T4	3		T47	1		T65	7
valid_sources[0x02]	4812	1			T4	2		T6	2		T24	5
valid_sources[0x03]	1833	1			T3	1		T4	1		T7	1
valid_sources[0x04]	1826	1			T3	1		T6	4		T7	2
valid_sources[0x05]	4560	1			T4	1		T7	4		T14	2
valid_sources[0x06]	2006	1			T1	1		T3	3		T4	2
valid_sources[0x07]	2825	1			T4	1		T14	1		T47	1
valid_sources[0x08]	1803	1			T4	1		T14	1		T27	1
valid_sources[0x09]	1779	1			T4	1		T6	3		T24	10
valid_sources[0x0a]	1838	1			T4	2		T6	6		T7	1
valid_sources[0x0b]	5742	1			T4	2		T7	1		T24	6
valid_sources[0x0c]	2311	1			T3	1		T4	2		T24	2
valid_sources[0x0d]	2036	1			T4	2		T6	1		T14	1
valid_sources[0x0e]	2088	1			T4	3		T6	1		T24	2
valid_sources[0x0f]	2029	1			T4	2		T7	2		T65	1
valid_sources[0x10]	1987	1			T4	1		T7	1		T24	2
valid_sources[0x11]	2120	1			T4	1		T24	4		T14	2
valid_sources[0x12]	1771	1			T4	4		T7	1		T24	4
valid_sources[0x13]	1717	1			T6	1		T29	7		T28	4
valid_sources[0x14]	1777	1			T3	2		T24	3		T47	1
valid_sources[0x15]	1923	1			T6	1		T7	2		T14	1
valid_sources[0x16]	2213	1			T3	1		T4	2		T7	4
valid_sources[0x17]	1709	1			T6	5		T7	1		T14	2
valid_sources[0x18]	2481	1			T3	2		T7	1		T24	8
valid_sources[0x19]	4477	1			T4	2		T6	1		T65	1
valid_sources[0x1a]	1940	1			T24	2		T47	1		T65	5
valid_sources[0x1b]	2474	1			T4	1		T6	1		T7	1
valid_sources[0x1c]	1930	1			T7	2		T24	2		T20	1
valid_sources[0x1d]	2269	1			T4	1		T7	2		T14	1
valid_sources[0x1e]	2026	1			T3	1		T4	2		T24	4
valid_sources[0x1f]	1789	1			T4	1		T24	1		T20	2
valid_sources[0x20]	1663	1			T1	1		T4	1		T7	2
valid_sources[0x21]	2412	1			T3	6		T4	1		T20	1
valid_sources[0x22]	2078	1			T3	2		T24	1		T20	1
valid_sources[0x23]	2002	1			T14	2		T20	3		T65	7
valid_sources[0x24]	1964	1			T4	4		T7	1		T24	1
valid_sources[0x25]	2807	1			T1	1		T4	4		T6	1
valid_sources[0x26]	2008	1			T1	1		T7	1		T14	1
valid_sources[0x27]	1773	1			T1	1		T4	2		T24	6
valid_sources[0x28]	1794	1			T3	4		T4	4		T7	1
valid_sources[0x29]	1938	1			T3	2		T7	1		T47	1
valid_sources[0x2a]	2311	1			T4	1		T6	1		T7	1
valid_sources[0x2b]	1776	1			T1	1		T4	1		T6	1
valid_sources[0x2c]	1839	1			T6	3		T7	2		T24	2
valid_sources[0x2d]	2013	1			T3	1		T4	4		T6	2
valid_sources[0x2e]	3560	1			T4	4		T20	1		T29	9
valid_sources[0x2f]	1778	1			T4	5		T6	2		T24	1
valid_sources[0x30]	1603	1			T3	1		T27	2		T171	1
valid_sources[0x31]	1733	1			T4	2		T6	2		T7	1
valid_sources[0x32]	1856	1			T3	2		T4	1		T7	1
valid_sources[0x33]	4070	1			T4	1		T6	5		T20	1
valid_sources[0x34]	11586	1			T4	1		T24	3		T14	1
valid_sources[0x35]	1944	1			T3	1		T4	5		T7	1
valid_sources[0x36]	2002	1			T3	1		T65	3		T27	1
valid_sources[0x37]	1572	1			T4	3		T24	8		T14	2
valid_sources[0x38]	1873	1			T1	1		T29	10		T51	3
valid_sources[0x39]	3513	1			T4	3		T14	1		T20	1
valid_sources[0x3a]	3163	1			T4	1		T24	2		T65	2
valid_sources[0x3b]	2154	1			T1	2		T3	2		T4	2
valid_sources[0x3c]	1819	1			T4	3		T7	3		T24	3
valid_sources[0x3d]	1708	1			T3	2		T4	3		T14	2
valid_sources[0x3e]	2310	1			T6	3		T15	83		T24	4
valid_sources[0x3f]	1915	1			T3	2		T4	1		T8	11
valid_sources[0x40]	8822	1			T3	4		T6	1		T24	2
valid_sources[0x41]	2996	1			T4	3		T6	1		T20	1
valid_sources[0x42]	2213	1			T1	1		T4	2		T20	1
valid_sources[0x43]	1821	1			T6	3		T7	1		T47	1
valid_sources[0x44]	1935	1			T27	1		T171	2		T29	9
valid_sources[0x45]	1907	1			T1	1		T3	1		T7	1
valid_sources[0x46]	2070	1			T3	2		T4	3		T7	2
valid_sources[0x47]	1865	1			T7	1		T24	2		T29	7
valid_sources[0x48]	2210	1			T1	2		T4	2		T6	12
valid_sources[0x49]	2044	1			T2	244		T4	1		T6	1
valid_sources[0x4a]	1852	1			T4	1		T20	1		T47	1
valid_sources[0x4b]	2703	1			T4	2		T8	4		T20	1
valid_sources[0x4c]	20222	1			T4	1		T24	1		T47	3
valid_sources[0x4d]	8178	1			T3	2		T4	1		T24	2
valid_sources[0x4e]	1914	1			T3	2		T4	4		T7	1
valid_sources[0x4f]	1790	1			T3	1		T24	1		T47	2
valid_sources[0x50]	2066	1			T3	1		T4	1		T7	2
valid_sources[0x51]	2061	1			T3	3		T4	3		T6	1
valid_sources[0x52]	3720	1			T14	1		T65	1		T29	7
valid_sources[0x53]	3048	1			T3	1		T4	1		T6	5
valid_sources[0x54]	1584	1			T4	4		T6	3		T7	2
valid_sources[0x55]	1803	1			T7	2		T14	3		T20	1
valid_sources[0x56]	2075	1			T1	1		T5	1		T24	1
valid_sources[0x57]	1605	1			T4	2		T6	6		T7	1
valid_sources[0x58]	2852	1			T7	2		T14	1		T20	1
valid_sources[0x59]	1743	1			T1	1		T3	1		T4	3
valid_sources[0x5a]	2158	1			T3	3		T6	5		T24	2
valid_sources[0x5b]	2142	1			T3	1		T6	1		T24	9
valid_sources[0x5c]	1910	1			T4	2		T47	1		T29	8
valid_sources[0x5d]	6542	1			T4	1		T7	3		T24	5
valid_sources[0x5e]	1849	1			T3	1		T47	2		T82	1
valid_sources[0x5f]	2017	1			T3	9		T4	2		T6	4
valid_sources[0x60]	1714	1			T4	1		T7	2		T14	1
valid_sources[0x61]	1782	1			T4	1		T7	1		T24	6
valid_sources[0x62]	1704	1			T4	2		T20	1		T29	3
valid_sources[0x63]	1867	1			T5	2		T7	1		T29	5
valid_sources[0x64]	2093	1			T3	4		T24	4		T27	1
valid_sources[0x65]	1793	1			T3	3		T4	6		T7	2
valid_sources[0x66]	2062	1			T4	2		T6	2		T24	1
valid_sources[0x67]	1946	1			T4	1		T5	1		T24	11
valid_sources[0x68]	1907	1			T3	4		T4	1		T20	1
valid_sources[0x69]	1885	1			T3	2		T4	1		T6	7
valid_sources[0x6a]	1847	1			T3	1		T4	4		T7	4
valid_sources[0x6b]	2081	1			T4	1		T20	2		T27	2
valid_sources[0x6c]	2543	1			T4	4		T6	2		T9	107
valid_sources[0x6d]	1834	1			T4	1		T7	1		T24	2
valid_sources[0x6e]	1865	1			T3	7		T4	1		T171	1
valid_sources[0x6f]	1912	1			T4	3		T6	9		T24	2
valid_sources[0x70]	1988	1			T7	2		T24	3		T14	3
valid_sources[0x71]	1832	1			T7	2		T171	1		T29	5
valid_sources[0x72]	1922	1			T7	2		T24	4		T20	1
valid_sources[0x73]	15426	1			T1	1		T3	12		T4	1
valid_sources[0x74]	1590	1			T3	2		T4	1		T6	1
valid_sources[0x75]	1810	1			T6	1		T7	1		T24	5
valid_sources[0x76]	1858	1			T4	3		T6	2		T24	3
valid_sources[0x77]	1799	1			T5	2		T65	1		T171	1
valid_sources[0x78]	2197	1			T10	24		T24	1		T20	1
valid_sources[0x79]	1603	1			T3	2		T4	2		T20	1
valid_sources[0x7a]	4049	1			T3	1		T4	1		T24	1
valid_sources[0x7b]	1876	1			T24	3		T29	5		T28	5
valid_sources[0x7c]	8572	1			T4	1		T5	2		T7	1
valid_sources[0x7d]	1965	1			T6	1		T24	11		T20	1
valid_sources[0x7e]	1784	1			T3	3		T24	1		T14	3
valid_sources[0x7f]	1861	1			T7	1		T29	6		T28	4
valid_sources[0x80]	7435	1			T4	1		T5	1		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

148530

1

T1

7

T2

15

T3

75

values[0x0]

all_enables

biggest_size

44652

1

T1

1

T2

7

T3

1

values[0x1]

all_enables

biggest_size

26069

1

T2

5

T3

2

T4

17