SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34960 | 1 | T29 | 415 | T28 | 293 | T61 | 300 | ||||
others[1] | 35039 | 1 | T27 | 1 | T29 | 400 | T28 | 332 | ||||
others[2] | 35200 | 1 | T29 | 375 | T28 | 308 | T61 | 330 | ||||
others[3] | 58199 | 1 | T3 | 1 | T29 | 664 | T28 | 493 | ||||
false | 13370 | 1 | T3 | 3 | T27 | 2 | T29 | 50 | ||||
true | 21350 | 1 | T1 | 1 | T2 | 1 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35097 | 1 | T29 | 399 | T28 | 326 | T61 | 325 | ||||
others[1] | 35211 | 1 | T3 | 2 | T29 | 405 | T28 | 312 | ||||
others[2] | 34780 | 1 | T29 | 399 | T28 | 289 | T61 | 317 | ||||
others[3] | 58285 | 1 | T27 | 1 | T29 | 667 | T28 | 466 | ||||
false | 9270 | 1 | T3 | 3 | T27 | 2 | T29 | 50 | ||||
true | 17317 | 1 | T1 | 1 | T2 | 1 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 534 | 1 | T2 | 5 | T3 | 1 | T9 | 2 | ||||
others[1] | 528 | 1 | T2 | 6 | T170 | 3 | T42 | 1 | ||||
others[2] | 548 | 1 | T2 | 5 | T9 | 2 | T41 | 2 | ||||
others[3] | 855 | 1 | T2 | 9 | T20 | 1 | T41 | 1 | ||||
false | 9338 | 1 | T1 | 1 | T2 | 4 | T3 | 6 | ||||
true | 2538 | 1 | T2 | 2 | T3 | 4 | T9 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |