Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17246115	25078	0	0
intr_enable_rd_A	17246115	19524	0	0
reset_en_rd_A	17246115	1392	0	0
reset_en_regwen_rd_A	17246115	1318	0	0
wake_info_capture_dis_rd_A	17246115	1283	0	0
wakeup_en_rd_A	17246115	2066	0	0
wakeup_en_regwen_rd_A	17246115	1310	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17246115	25078	0	0
T13	1319	0	0	0
T16	97006	12	0	0
T25	0	22	0	0
T26	0	5	0	0
T53	1802	0	0	0
T58	0	10	0	0
T76	0	33	0	0
T122	0	19	0	0
T123	0	26	0	0
T124	0	22	0	0
T125	0	1	0	0
T126	0	22	0	0
T127	73879	0	0	0
T128	2676	0	0	0
T129	59384	0	0	0
T130	847	0	0	0
T131	53796	0	0	0
T132	2517	0	0	0
T133	15181	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17246115	19524	0	0
T2	4335	119	0	0
T3	4651	0	0	0
T4	4375	0	0	0
T5	1093	0	0	0
T6	7361	45	0	0
T7	5322	12	0	0
T8	1835	7	0	0
T9	7877	0	0	0
T10	1217	0	0	0
T15	1808	26	0	0
T28	0	179	0	0
T65	0	33	0	0
T66	0	9	0	0
T80	0	5	0	0
T81	0	6	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17246115	1392	0	0
T13	1319	0	0	0
T16	97006	4	0	0
T53	1802	0	0	0
T68	0	108	0	0
T78	0	14	0	0
T101	0	9	0	0
T102	0	82	0	0
T118	0	7	0	0
T123	0	7	0	0
T127	73879	0	0	0
T128	2676	0	0	0
T129	59384	0	0	0
T130	847	0	0	0
T131	53796	0	0	0
T132	2517	0	0	0
T133	15181	0	0	0
T134	0	8	0	0
T135	0	37	0	0
T136	0	49	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17246115	1318	0	0
T68	0	101	0	0
T78	0	14	0	0
T101	0	9	0	0
T102	0	58	0	0
T118	0	1	0	0
T123	623298	8	0	0
T134	0	9	0	0
T135	0	28	0	0
T136	0	36	0	0
T137	0	51	0	0
T138	26218	0	0	0
T139	2838	0	0	0
T140	2621	0	0	0
T141	6038	0	0	0
T142	4093	0	0	0
T143	1581	0	0	0
T144	3471	0	0	0
T145	54462	0	0	0
T146	10357	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17246115	1283	0	0
T13	1319	0	0	0
T16	97006	9	0	0
T53	1802	0	0	0
T68	0	140	0	0
T78	0	44	0	0
T101	0	2	0	0
T102	0	54	0	0
T118	0	3	0	0
T127	73879	0	0	0
T128	2676	0	0	0
T129	59384	0	0	0
T130	847	0	0	0
T131	53796	0	0	0
T132	2517	0	0	0
T133	15181	0	0	0
T134	0	1	0	0
T135	0	23	0	0
T136	0	38	0	0
T137	0	41	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17246115	2066	0	0
T13	1319	0	0	0
T16	97006	13	0	0
T53	1802	0	0	0
T68	0	106	0	0
T78	0	28	0	0
T101	0	25	0	0
T102	0	56	0	0
T118	0	19	0	0
T123	0	3	0	0
T127	73879	0	0	0
T128	2676	0	0	0
T129	59384	0	0	0
T130	847	0	0	0
T131	53796	0	0	0
T132	2517	0	0	0
T133	15181	0	0	0
T134	0	8	0	0
T135	0	13	0	0
T136	0	142	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17246115	1310	0	0
T13	1319	0	0	0
T16	97006	9	0	0
T53	1802	0	0	0
T68	0	116	0	0
T78	0	12	0	0
T101	0	10	0	0
T102	0	59	0	0
T118	0	4	0	0
T123	0	9	0	0
T127	73879	0	0	0
T128	2676	0	0	0
T129	59384	0	0	0
T130	847	0	0	0
T131	53796	0	0	0
T132	2517	0	0	0
T133	15181	0	0	0
T134	0	1	0	0
T135	0	25	0	0
T136	0	29	0	0