Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	16596606	39655	0	0
RomAllowCheckGoodState_A	16596606	39705	0	0
RomBlockActiveState_A	16596606	28928	0	0
RomBlockCheckGoodState_A	16596606	355508	0	0
RomIntgChkDisFalse_A	16596606	16118949	0	0
RomIntgChkDisTrue_A	16596606	104570	0	0
RstreqChkEsctimeout_A	16596606	2806	0	0
RstreqChkFsmterm_A	16596606	160	0	0
RstreqChkGlbesc_A	16596606	2807	0	0
RstreqChkMainpd_A	16596606	703946	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	39655	0	0
T1	1454	3	0	0
T2	4335	3	0	0
T3	4651	6	0	0
T4	4375	40	0	0
T5	1093	3	0	0
T6	7361	18	0	0
T7	5322	12	0	0
T8	1835	3	0	0
T9	7877	13	0	0
T10	1217	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	39705	0	0
T1	1454	3	0	0
T2	4335	3	0	0
T3	4651	6	0	0
T4	4375	40	0	0
T5	1093	3	0	0
T6	7361	18	0	0
T7	5322	12	0	0
T8	1835	3	0	0
T9	7877	14	0	0
T10	1217	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	28928	0	0
T3	4651	1158	0	0
T4	4375	0	0	0
T5	1093	0	0	0
T6	7361	0	0	0
T7	5322	0	0	0
T8	1835	0	0	0
T9	7877	0	0	0
T10	1217	0	0	0
T15	1808	0	0	0
T24	17931	0	0	0
T27	0	130	0	0
T49	0	163	0	0
T147	0	13	0	0
T148	0	1424	0	0
T149	0	480	0	0
T150	0	11	0	0
T151	0	8	0	0
T152	0	294	0	0
T153	0	996	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	355508	0	0
T3	4651	998	0	0
T4	4375	0	0	0
T5	1093	0	0	0
T6	7361	0	0	0
T7	5322	0	0	0
T8	1835	0	0	0
T9	7877	0	0	0
T10	1217	0	0	0
T15	1808	0	0	0
T16	0	1193	0	0
T24	17931	0	0	0
T27	0	33	0	0
T28	0	1942	0	0
T29	0	4090	0	0
T49	0	6	0	0
T51	0	343	0	0
T61	0	3984	0	0
T147	0	1286	0	0
T154	0	2251	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	16118949	0	0
T1	1454	1378	0	0
T2	4335	4244	0	0
T3	4651	3503	0	0
T4	4375	4091	0	0
T5	1093	1042	0	0
T6	7361	7293	0	0
T7	5322	5252	0	0
T8	1835	1769	0	0
T9	7877	6916	0	0
T10	1217	1130	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	104570	0	0
T3	4651	1088	0	0
T4	4375	0	0	0
T5	1093	0	0	0
T6	7361	0	0	0
T7	5322	0	0	0
T8	1835	0	0	0
T9	7877	0	0	0
T10	1217	0	0	0
T15	1808	0	0	0
T24	17931	0	0	0
T27	0	443	0	0
T28	0	84	0	0
T49	0	57	0	0
T61	0	2000	0	0
T129	0	3867	0	0
T131	0	1206	0	0
T148	0	515	0	0
T149	0	1251	0	0
T155	0	360	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	2806	0	0
T3	4651	2	0	0
T4	4375	0	0	0
T5	1093	0	0	0
T6	7361	0	0	0
T7	5322	0	0	0
T8	1835	0	0	0
T9	7877	5	0	0
T10	1217	0	0	0
T11	0	1	0	0
T14	0	2	0	0
T15	1808	0	0	0
T20	0	7	0	0
T24	17931	0	0	0
T27	0	3	0	0
T41	0	7	0	0
T42	0	5	0	0
T48	0	4	0	0
T50	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	160	0	0
T21	13442	20	0	0
T22	0	40	0	0
T23	0	40	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	95385	0	0	0
T33	7692	0	0	0
T34	1962	0	0	0
T35	1951	0	0	0
T36	1372	0	0	0
T37	16966	0	0	0
T38	17445	0	0	0
T39	3873	0	0	0
T40	1205	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	2807	0	0
T3	4651	2	0	0
T4	4375	0	0	0
T5	1093	0	0	0
T6	7361	0	0	0
T7	5322	0	0	0
T8	1835	0	0	0
T9	7877	5	0	0
T10	1217	0	0	0
T11	0	1	0	0
T14	0	2	0	0
T15	1808	0	0	0
T20	0	7	0	0
T24	17931	0	0	0
T27	0	3	0	0
T41	0	7	0	0
T42	0	5	0	0
T48	0	4	0	0
T50	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16596606	703946	0	0
T9	7877	279	0	0
T10	1217	0	0	0
T11	15194	0	0	0
T14	4103	251	0	0
T15	1808	0	0	0
T17	0	22	0	0
T18	0	27	0	0
T20	3184	121	0	0
T24	17931	0	0	0
T27	0	63	0	0
T29	0	5939	0	0
T41	0	85	0	0
T42	0	123	0	0
T43	0	110	0	0
T45	5925	0	0	0
T46	2169	0	0	0
T47	4375	0	0	0