Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

Group : pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
WakeupAonTimer_intr_cg	100.00	1	100	1	64	64
WakeupDbgCable_intr_cg	100.00	1	100	1	64	64
WakeupPin_intr_cg	100.00	1	100	1	64	64
WakeupSensorCtrl_intr_cg	100.00	1	100	1	64	64
WakeupSysrst_intr_cg	100.00	1	100	1	64	64
WakeupUsb_intr_cg	100.00	1	100	1	64	64

---

Group Instance : WakeupAonTimer_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupAonTimer_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupAonTimer_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupAonTimer_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupDbgCable_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupDbgCable_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupDbgCable_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupDbgCable_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupPin_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupPin_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupPin_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupPin_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSensorCtrl_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSensorCtrl_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSensorCtrl_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSensorCtrl_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSysrst_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSysrst_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSysrst_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSysrst_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupUsb_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupUsb_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupUsb_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupUsb_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34421

1

T1

13

T2

3

T3

2

auto[1]

8948

1

T3

1

T6

1

T8

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32949

1

T1

13

T2

3

T3

2

auto[1]

10420

1

T3

1

T6

1

T8

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24139

1

T1

12

T2

3

T3

2

auto[1]

19230

1

T1

1

T3

1

T5

3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18740

1

T1

13

T2

3

T3

1

auto[1]

24629

1

T3

2

T6

1

T8

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11233

1

T1

12

T2

3

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

8591

1

T8

6

T10

1

T51

2

auto[0]

auto[1]

auto[0]

auto[0]

5719

1

T1

1

T5

3

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

2167

1

T12

2

T13

3

T14

51

auto[1]

auto[0]

auto[0]

auto[0]

864

1

T40

4

T42

2

T14

6

auto[1]

auto[0]

auto[1]

auto[0]

3451

1

T3

1

T8

2

T51

1

auto[1]

auto[1]

auto[0]

auto[0]

924

1

T8

4

T26

6

T27

4

auto[1]

auto[1]

auto[1]

auto[1]

3709

1

T6

1

T8

1

T10

1

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34177

1

T1

13

T2

3

T3

2

auto[1]

9192

1

T3

1

T6

1

T8

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32949

1

T1

13

T2

3

T3

2

auto[1]

10420

1

T3

1

T6

1

T8

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24139

1

T1

12

T2

3

T3

2

auto[1]

19230

1

T1

1

T3

1

T5

3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18740

1

T1

13

T2

3

T3

1

auto[1]

24629

1

T3

2

T6

1

T8

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11241

1

T1

12

T2

3

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

8513

1

T3

1

T8

6

T51

1

auto[0]

auto[1]

auto[0]

auto[0]

5689

1

T1

1

T5

3

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

2167

1

T12

2

T13

3

T14

51

auto[1]

auto[0]

auto[0]

auto[0]

856

1

T27

6

T39

2

T40

4

auto[1]

auto[0]

auto[1]

auto[0]

3529

1

T8

2

T10

1

T51

2

auto[1]

auto[1]

auto[0]

auto[0]

954

1

T8

4

T27

4

T39

4

auto[1]

auto[1]

auto[1]

auto[1]

3853

1

T3

1

T6

1

T8

2

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34470

1

T1

13

T2

3

T3

3

auto[1]

8899

1

T6

1

T8

10

T51

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32949

1

T1

13

T2

3

T3

2

auto[1]

10420

1

T3

1

T6

1

T8

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24139

1

T1

12

T2

3

T3

2

auto[1]

19230

1

T1

1

T3

1

T5

3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18740

1

T1

13

T2

3

T3

1

auto[1]

24629

1

T3

2

T6

1

T8

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11263

1

T1

12

T2

3

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

8566

1

T3

1

T8

4

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

5719

1

T1

1

T5

3

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

2167

1

T12

2

T13

3

T14

51

auto[1]

auto[0]

auto[0]

auto[0]

834

1

T26

2

T27

4

T39

4

auto[1]

auto[0]

auto[1]

auto[0]

3476

1

T8

4

T51

1

T26

1

auto[1]

auto[1]

auto[0]

auto[0]

924

1

T8

2

T27

2

T39

10

auto[1]

auto[1]

auto[1]

auto[1]

3665

1

T6

1

T8

4

T51

3

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34541

1

T1

13

T2

3

T3

3

auto[1]

8828

1

T8

10

T51

4

T26

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32949

1

T1

13

T2

3

T3

2

auto[1]

10420

1

T3

1

T6

1

T8

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24139

1

T1

12

T2

3

T3

2

auto[1]

19230

1

T1

1

T3

1

T5

3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18740

1

T1

13

T2

3

T3

1

auto[1]

24629

1

T3

2

T6

1

T8

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11257

1

T1

12

T2

3

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

8708

1

T3

1

T8

6

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

5702

1

T1

1

T5

3

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

2167

1

T12

2

T13

3

T14

51

auto[1]

auto[0]

auto[0]

auto[0]

840

1

T27

2

T39

2

T40

4

auto[1]

auto[0]

auto[1]

auto[0]

3334

1

T8

2

T51

2

T26

1

auto[1]

auto[1]

auto[0]

auto[0]

941

1

T8

8

T26

4

T27

4

auto[1]

auto[1]

auto[1]

auto[1]

3713

1

T51

2

T26

4

T62

3

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34543

1

T1

13

T2

3

T3

2

auto[1]

8826

1

T3

1

T6

1

T8

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32949

1

T1

13

T2

3

T3

2

auto[1]

10420

1

T3

1

T6

1

T8

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24139

1

T1

12

T2

3

T3

2

auto[1]

19230

1

T1

1

T3

1

T5

3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18740

1

T1

13

T2

3

T3

1

auto[1]

24629

1

T3

2

T6

1

T8

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11275

1

T1

12

T2

3

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

8591

1

T3

1

T8

8

T51

2

auto[0]

auto[1]

auto[0]

auto[0]

5847

1

T1

1

T5

3

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

2167

1

T12

2

T13

3

T14

51

auto[1]

auto[0]

auto[0]

auto[0]

822

1

T27

4

T40

8

T13

2

auto[1]

auto[0]

auto[1]

auto[0]

3451

1

T10

1

T51

1

T26

2

auto[1]

auto[1]

auto[0]

auto[0]

796

1

T8

4

T27

6

T39

2

auto[1]

auto[1]

auto[1]

auto[1]

3757

1

T3

1

T6

1

T8

4

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34367

1

T1

13

T2

3

T3

1

auto[1]

9002

1

T3

2

T8

3

T10

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32949

1

T1

13

T2

3

T3

2

auto[1]

10420

1

T3

1

T6

1

T8

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24139

1

T1

12

T2

3

T3

2

auto[1]

19230

1

T1

1

T3

1

T5

3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18740

1

T1

13

T2

3

T3

1

auto[1]

24629

1

T3

2

T6

1

T8

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

11219

1

T1

12

T2

3

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

8462

1

T8

6

T10

1

T51

1

auto[0]

auto[1]

auto[0]

auto[0]

5843

1

T1

1

T5

3

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

2167

1

T12

2

T13

3

T14

51

auto[1]

auto[0]

auto[0]

auto[0]

878

1

T26

4

T27

4

T39

6

auto[1]

auto[0]

auto[1]

auto[0]

3580

1

T3

1

T8

2

T51

2

auto[1]

auto[1]

auto[0]

auto[0]

800

1

T26

8

T27

8

T39

2

auto[1]

auto[1]

auto[1]

auto[1]

3744

1

T3

1

T8

1

T10

1

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded