Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	440763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

213867

1

T1

45

T3

34

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	412774	1			T1	62		T2	1		T3	56
values[0x0]	120260	1			T1	17		T3	11		T5	14
values[0x1]	121596	1			T1	16		T3	7		T5	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	349280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

305350

1

T1

54

T2

1

T3

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2142	1			T6	2		T8	1		T62	1
valid_sources[0x01]	2180	1			T8	2		T26	3		T62	1
valid_sources[0x02]	2310	1			T26	2		T62	2		T27	6
valid_sources[0x03]	2246	1			T8	7		T52	2		T27	2
valid_sources[0x04]	2259	1			T26	1		T27	4		T85	1
valid_sources[0x05]	2680	1			T26	3		T62	1		T52	1
valid_sources[0x06]	2401	1			T8	2		T25	1		T26	6
valid_sources[0x07]	4185	1			T8	2		T26	5		T52	4
valid_sources[0x08]	2348	1			T27	2		T63	2		T154	9
valid_sources[0x09]	2577	1			T8	4		T26	5		T52	1
valid_sources[0x0a]	2330	1			T8	1		T25	3		T27	6
valid_sources[0x0b]	2326	1			T26	7		T62	3		T27	10
valid_sources[0x0c]	2287	1			T26	3		T62	1		T52	1
valid_sources[0x0d]	2783	1			T26	1		T62	1		T63	4
valid_sources[0x0e]	2849	1			T8	1		T25	1		T26	1
valid_sources[0x0f]	2182	1			T26	5		T62	2		T27	5
valid_sources[0x10]	2256	1			T26	6		T27	4		T63	1
valid_sources[0x11]	2126	1			T1	95		T8	2		T26	10
valid_sources[0x12]	2019	1			T26	1		T62	2		T27	1
valid_sources[0x13]	2320	1			T8	2		T62	2		T27	3
valid_sources[0x14]	3773	1			T62	1		T27	4		T63	8
valid_sources[0x15]	2028	1			T27	3		T63	3		T85	1
valid_sources[0x16]	2158	1			T25	1		T26	3		T62	3
valid_sources[0x17]	2295	1			T26	4		T62	5		T27	6
valid_sources[0x18]	2125	1			T27	2		T63	1		T85	1
valid_sources[0x19]	2165	1			T25	3		T26	1		T27	5
valid_sources[0x1a]	2140	1			T8	2		T26	2		T62	4
valid_sources[0x1b]	2227	1			T8	1		T26	2		T27	5
valid_sources[0x1c]	2220	1			T8	2		T62	3		T27	3
valid_sources[0x1d]	2113	1			T8	2		T26	5		T85	1
valid_sources[0x1e]	2506	1			T62	7		T27	1		T63	1
valid_sources[0x1f]	2470	1			T25	1		T62	1		T27	4
valid_sources[0x20]	2725	1			T8	2		T62	3		T27	1
valid_sources[0x21]	2376	1			T62	1		T27	7		T63	1
valid_sources[0x22]	2127	1			T26	5		T27	3		T63	1
valid_sources[0x23]	2286	1			T8	4		T26	3		T62	1
valid_sources[0x24]	2245	1			T8	2		T62	4		T27	3
valid_sources[0x25]	2145	1			T8	1		T27	7		T39	2
valid_sources[0x26]	2120	1			T26	2		T62	2		T27	3
valid_sources[0x27]	2269	1			T62	1		T27	7		T63	1
valid_sources[0x28]	2556	1			T8	3		T25	1		T62	1
valid_sources[0x29]	2496	1			T8	2		T25	1		T62	2
valid_sources[0x2a]	2299	1			T8	1		T26	2		T62	3
valid_sources[0x2b]	2147	1			T27	2		T154	1		T39	10
valid_sources[0x2c]	2463	1			T26	8		T62	5		T27	1
valid_sources[0x2d]	3035	1			T62	2		T27	3		T63	1
valid_sources[0x2e]	2409	1			T8	1		T26	2		T12	3
valid_sources[0x2f]	2463	1			T8	3		T26	1		T52	1
valid_sources[0x30]	2114	1			T10	1		T26	3		T27	3
valid_sources[0x31]	2422	1			T8	1		T27	5		T63	1
valid_sources[0x32]	2292	1			T62	2		T27	2		T63	3
valid_sources[0x33]	2385	1			T25	1		T62	3		T27	9
valid_sources[0x34]	2218	1			T8	2		T25	2		T62	2
valid_sources[0x35]	2164	1			T8	1		T26	1		T52	1
valid_sources[0x36]	2138	1			T8	1		T10	1		T26	1
valid_sources[0x37]	8299	1			T26	2		T12	1		T62	1
valid_sources[0x38]	2340	1			T6	1		T8	3		T26	11
valid_sources[0x39]	2509	1			T8	2		T26	5		T62	2
valid_sources[0x3a]	2542	1			T26	10		T47	1		T27	2
valid_sources[0x3b]	2203	1			T8	3		T12	1		T62	1
valid_sources[0x3c]	3230	1			T8	1		T25	1		T26	1
valid_sources[0x3d]	2238	1			T25	1		T26	1		T62	6
valid_sources[0x3e]	2189	1			T26	4		T62	2		T63	2
valid_sources[0x3f]	2227	1			T52	1		T27	5		T63	3
valid_sources[0x40]	2348	1			T62	2		T27	3		T85	1
valid_sources[0x41]	2701	1			T8	1		T25	1		T26	3
valid_sources[0x42]	2377	1			T8	3		T26	4		T62	3
valid_sources[0x43]	2225	1			T8	2		T26	10		T62	4
valid_sources[0x44]	2165	1			T8	2		T27	9		T39	3
valid_sources[0x45]	2321	1			T8	3		T27	3		T63	1
valid_sources[0x46]	2535	1			T25	1		T26	1		T62	5
valid_sources[0x47]	2413	1			T8	3		T26	8		T27	3
valid_sources[0x48]	3292	1			T8	3		T25	1		T27	5
valid_sources[0x49]	2555	1			T26	1		T62	2		T27	8
valid_sources[0x4a]	2598	1			T7	1		T27	3		T63	1
valid_sources[0x4b]	2135	1			T8	1		T26	2		T62	1
valid_sources[0x4c]	2555	1			T26	10		T27	2		T154	2
valid_sources[0x4d]	2729	1			T26	8		T27	7		T63	1
valid_sources[0x4e]	2241	1			T6	1		T25	2		T27	5
valid_sources[0x4f]	4889	1			T8	4		T25	3		T27	5
valid_sources[0x50]	2171	1			T62	4		T27	4		T63	2
valid_sources[0x51]	2279	1			T6	1		T8	2		T62	4
valid_sources[0x52]	3455	1			T8	2		T25	1		T26	7
valid_sources[0x53]	2141	1			T8	1		T25	1		T27	5
valid_sources[0x54]	2642	1			T6	1		T8	3		T26	3
valid_sources[0x55]	2284	1			T6	1		T8	1		T26	1
valid_sources[0x56]	2290	1			T8	2		T26	3		T62	1
valid_sources[0x57]	2347	1			T8	6		T26	3		T27	1
valid_sources[0x58]	2612	1			T8	6		T27	3		T63	2
valid_sources[0x59]	2285	1			T25	1		T27	2		T154	2
valid_sources[0x5a]	2228	1			T62	3		T11	1		T52	1
valid_sources[0x5b]	2697	1			T8	6		T26	18		T12	1
valid_sources[0x5c]	2324	1			T6	1		T26	9		T62	2
valid_sources[0x5d]	2327	1			T6	1		T62	5		T27	3
valid_sources[0x5e]	2336	1			T26	2		T52	1		T27	3
valid_sources[0x5f]	2125	1			T8	4		T26	7		T27	3
valid_sources[0x60]	2819	1			T8	4		T25	1		T27	3
valid_sources[0x61]	2720	1			T26	1		T62	5		T27	4
valid_sources[0x62]	2315	1			T26	2		T62	1		T27	3
valid_sources[0x63]	2117	1			T25	1		T27	3		T63	3
valid_sources[0x64]	2066	1			T26	2		T62	1		T27	5
valid_sources[0x65]	2426	1			T8	1		T10	4		T26	10
valid_sources[0x66]	2505	1			T8	2		T10	1		T25	1
valid_sources[0x67]	2249	1			T8	5		T26	1		T27	3
valid_sources[0x68]	2442	1			T8	2		T25	1		T62	2
valid_sources[0x69]	2103	1			T26	1		T12	3		T52	1
valid_sources[0x6a]	3549	1			T10	1		T26	8		T27	5
valid_sources[0x6b]	2330	1			T2	1		T4	1		T26	2
valid_sources[0x6c]	2280	1			T10	1		T25	1		T27	1
valid_sources[0x6d]	2381	1			T27	3		T63	1		T85	1
valid_sources[0x6e]	2213	1			T25	1		T62	2		T27	2
valid_sources[0x6f]	4103	1			T6	1		T26	2		T27	2
valid_sources[0x70]	4206	1			T8	1		T26	2		T62	1
valid_sources[0x71]	2684	1			T6	1		T9	1		T26	5
valid_sources[0x72]	2010	1			T8	2		T25	3		T26	4
valid_sources[0x73]	2200	1			T25	1		T27	5		T154	3
valid_sources[0x74]	2137	1			T26	6		T62	2		T27	9
valid_sources[0x75]	2410	1			T25	1		T26	4		T52	1
valid_sources[0x76]	2279	1			T6	1		T8	3		T51	123
valid_sources[0x77]	2245	1			T8	1		T27	7		T63	2
valid_sources[0x78]	2113	1			T6	1		T8	1		T26	2
valid_sources[0x79]	3499	1			T8	1		T25	1		T26	1
valid_sources[0x7a]	2155	1			T27	4		T63	3		T39	2
valid_sources[0x7b]	2146	1			T25	1		T62	3		T27	2
valid_sources[0x7c]	2292	1			T25	1		T27	2		T63	2
valid_sources[0x7d]	2506	1			T8	2		T25	2		T62	3
valid_sources[0x7e]	2332	1			T8	1		T26	1		T62	4
valid_sources[0x7f]	2069	1			T26	3		T62	3		T63	1
valid_sources[0x80]	2274	1			T8	1		T10	2		T26	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

143232

1

T1

34

T3

27

T4

1

values[0x0]

all_enables

biggest_size

45495

1

T1

6

T3

6

T5

5

values[0x1]

all_enables

biggest_size

25140

1

T1

5

T3

1

T5

3