SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34954 | 1 | T27 | 384 | T39 | 382 | T40 | 366 | ||||
others[1] | 35155 | 1 | T27 | 383 | T39 | 423 | T40 | 396 | ||||
others[2] | 34888 | 1 | T27 | 408 | T39 | 398 | T40 | 430 | ||||
others[3] | 58571 | 1 | T27 | 689 | T39 | 672 | T40 | 673 | ||||
false | 14485 | 1 | T8 | 30 | T26 | 34 | T27 | 50 | ||||
true | 22712 | 1 | T1 | 12 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34843 | 1 | T27 | 391 | T39 | 403 | T40 | 405 | ||||
others[1] | 34881 | 1 | T27 | 394 | T39 | 395 | T40 | 385 | ||||
others[2] | 35215 | 1 | T27 | 417 | T39 | 409 | T40 | 409 | ||||
others[3] | 58475 | 1 | T27 | 667 | T39 | 667 | T40 | 667 | ||||
false | 9821 | 1 | T8 | 15 | T26 | 17 | T27 | 50 | ||||
true | 18137 | 1 | T1 | 12 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 616 | 1 | T41 | 1 | T141 | 7 | T53 | 1 | ||||
others[1] | 551 | 1 | T1 | 2 | T25 | 1 | T141 | 5 | ||||
others[2] | 521 | 1 | T41 | 4 | T141 | 4 | T53 | 1 | ||||
others[3] | 924 | 1 | T1 | 2 | T43 | 1 | T41 | 1 | ||||
false | 10112 | 1 | T1 | 19 | T2 | 2 | T3 | 1 | ||||
true | 2917 | 1 | T1 | 3 | T5 | 3 | T25 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |