Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18122312	14065	0	0
intr_enable_rd_A	18122312	23047	0	0
reset_en_rd_A	18122312	918	0	0
reset_en_regwen_rd_A	18122312	920	0	0
wake_info_capture_dis_rd_A	18122312	857	0	0
wakeup_en_rd_A	18122312	1563	0	0
wakeup_en_regwen_rd_A	18122312	813	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18122312	14065	0	0
T14	332840	4	0	0
T20	0	19	0	0
T21	0	13	0	0
T22	57216	0	0	0
T23	5616	0	0	0
T24	1601	0	0	0
T30	0	27	0	0
T55	1458	0	0	0
T59	0	99	0	0
T60	0	90	0	0
T68	8498	0	0	0
T80	0	2	0	0
T89	0	28	0	0
T135	0	4	0	0
T136	0	99	0	0
T137	8991	0	0	0
T138	3212	0	0	0
T139	59203	0	0	0
T140	7878	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18122312	23047	0	0
T11	2246	0	0	0
T12	1111	0	0	0
T25	3145	0	0	0
T26	18320	0	0	0
T27	21539	173	0	0
T41	0	80	0	0
T47	2544	0	0	0
T48	0	12	0	0
T51	3768	16	0	0
T52	3116	0	0	0
T62	19391	39	0	0
T63	9070	0	0	0
T66	0	42	0	0
T141	0	75	0	0
T142	0	14	0	0
T143	0	9	0	0
T144	0	118	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18122312	918	0	0
T14	332840	6	0	0
T22	57216	0	0	0
T23	5616	0	0	0
T24	1601	0	0	0
T55	1458	0	0	0
T56	0	28	0	0
T58	0	48	0	0
T68	8498	0	0	0
T77	0	36	0	0
T103	0	2	0	0
T112	0	2	0	0
T137	8991	0	0	0
T138	3212	0	0	0
T139	59203	0	0	0
T140	7878	0	0	0
T145	0	15	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	13	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18122312	920	0	0
T14	332840	7	0	0
T22	57216	0	0	0
T23	5616	0	0	0
T24	1601	0	0	0
T55	1458	0	0	0
T56	0	19	0	0
T58	0	29	0	0
T68	8498	0	0	0
T77	0	18	0	0
T112	0	3	0	0
T131	0	73	0	0
T137	8991	0	0	0
T138	3212	0	0	0
T139	59203	0	0	0
T140	7878	0	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	4	0	0
T148	0	9	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18122312	857	0	0
T14	332840	5	0	0
T22	57216	0	0	0
T23	5616	0	0	0
T24	1601	0	0	0
T55	1458	0	0	0
T56	0	12	0	0
T58	0	45	0	0
T68	8498	0	0	0
T77	0	14	0	0
T103	0	3	0	0
T112	0	8	0	0
T131	0	78	0	0
T137	8991	0	0	0
T138	3212	0	0	0
T139	59203	0	0	0
T140	7878	0	0	0
T145	0	5	0	0
T146	0	1	0	0
T147	0	13	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18122312	1563	0	0
T14	332840	9	0	0
T22	57216	0	0	0
T23	5616	0	0	0
T24	1601	0	0	0
T55	1458	0	0	0
T56	0	3	0	0
T58	0	159	0	0
T68	8498	0	0	0
T77	0	7	0	0
T82	0	26	0	0
T112	0	2	0	0
T131	0	64	0	0
T137	8991	0	0	0
T138	3212	0	0	0
T139	59203	0	0	0
T140	7878	0	0	0
T145	0	12	0	0
T146	0	6	0	0
T148	0	34	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18122312	813	0	0
T14	332840	9	0	0
T22	57216	0	0	0
T23	5616	0	0	0
T24	1601	0	0	0
T55	1458	0	0	0
T58	0	45	0	0
T68	8498	0	0	0
T82	0	39	0	0
T103	0	4	0	0
T112	0	1	0	0
T131	0	27	0	0
T137	8991	0	0	0
T138	3212	0	0	0
T139	59203	0	0	0
T140	7878	0	0	0
T145	0	7	0	0
T146	0	7	0	0
T147	0	1	0	0
T148	0	9	0	0