Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	17558838	38837	0	0
IoStatusRise_A	17558838	43164	0	0
MainStatusFall_A	17558838	38837	0	0
MainStatusRise_A	17558838	43164	0	0
UsbStatusFall_A	17558838	29814	0	0
UsbStatusRise_A	17558838	33439	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	38837	0	0
T1	7142	18	0	0
T2	625	1	0	0
T3	3027	2	0	0
T4	1236	0	0	0
T5	1046	5	0	0
T6	2712	2	0	0
T7	803	1	0	0
T8	7554	28	0	0
T9	1111	0	0	0
T10	2337	2	0	0
T25	0	8	0	0
T51	0	8	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	43164	0	0
T1	7142	19	0	0
T2	625	3	0	0
T3	3027	3	0	0
T4	1236	3	0	0
T5	1046	7	0	0
T6	2712	3	0	0
T7	803	3	0	0
T8	7554	30	0	0
T9	1111	2	0	0
T10	2337	3	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	38837	0	0
T1	7142	18	0	0
T2	625	1	0	0
T3	3027	2	0	0
T4	1236	0	0	0
T5	1046	5	0	0
T6	2712	2	0	0
T7	803	1	0	0
T8	7554	28	0	0
T9	1111	0	0	0
T10	2337	2	0	0
T25	0	8	0	0
T51	0	8	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	43164	0	0
T1	7142	19	0	0
T2	625	3	0	0
T3	3027	3	0	0
T4	1236	3	0	0
T5	1046	7	0	0
T6	2712	3	0	0
T7	803	3	0	0
T8	7554	30	0	0
T9	1111	2	0	0
T10	2337	3	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	29814	0	0
T1	7142	18	0	0
T2	625	1	0	0
T3	3027	1	0	0
T4	1236	0	0	0
T5	1046	5	0	0
T6	2712	2	0	0
T7	803	1	0	0
T8	7554	12	0	0
T9	1111	0	0	0
T10	2337	2	0	0
T25	0	8	0	0
T51	0	4	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	33439	0	0
T1	7142	19	0	0
T2	625	3	0	0
T3	3027	1	0	0
T4	1236	3	0	0
T5	1046	7	0	0
T6	2712	3	0	0
T7	803	3	0	0
T8	7554	14	0	0
T9	1111	2	0	0
T10	2337	3	0	0