Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	17558838	42782	0	0
RomAllowCheckGoodState_A	17558838	42831	0	0
RomBlockActiveState_A	17558838	32921	0	0
RomBlockCheckGoodState_A	17558838	354139	0	0
RomIntgChkDisFalse_A	17558838	17056084	0	0
RomIntgChkDisTrue_A	17558838	109214	0	0
RstreqChkEsctimeout_A	17558838	3069	0	0
RstreqChkFsmterm_A	17558838	140	0	0
RstreqChkGlbesc_A	17558838	3069	0	0
RstreqChkMainpd_A	17558838	765821	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	42782	0	0
T1	7142	12	0	0
T2	625	3	0	0
T3	3027	3	0	0
T4	1236	3	0	0
T5	1046	7	0	0
T6	2712	3	0	0
T7	803	3	0	0
T8	7554	30	0	0
T9	1111	2	0	0
T10	2337	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	42831	0	0
T1	7142	13	0	0
T2	625	3	0	0
T3	3027	3	0	0
T4	1236	3	0	0
T5	1046	7	0	0
T6	2712	3	0	0
T7	803	3	0	0
T8	7554	30	0	0
T9	1111	2	0	0
T10	2337	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	32921	0	0
T15	2017	0	0	0
T16	1434	0	0	0
T23	0	824	0	0
T24	0	295	0	0
T27	21539	14	0	0
T39	23231	12	0	0
T43	3398	0	0	0
T44	1350	0	0	0
T63	9070	0	0	0
T85	2385	0	0	0
T86	1522	0	0	0
T94	0	180	0	0
T149	0	1065	0	0
T150	0	920	0	0
T151	0	9	0	0
T152	0	285	0	0
T153	0	1197	0	0
T154	15619	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	354139	0	0
T8	7554	345	0	0
T9	1111	0	0	0
T10	2337	0	0	0
T11	2246	0	0	0
T12	1111	0	0	0
T13	0	413	0	0
T25	3145	0	0	0
T26	18320	390	0	0
T27	0	925	0	0
T39	0	1233	0	0
T40	0	1677	0	0
T42	0	322	0	0
T46	1214	0	0	0
T51	3768	0	0	0
T62	19391	0	0	0
T85	0	46	0	0
T155	0	91	0	0
T156	0	436	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	17056084	0	0
T1	7142	6180	0	0
T2	625	504	0	0
T3	3027	2936	0	0
T4	1236	1024	0	0
T5	1046	913	0	0
T6	2712	2629	0	0
T7	803	683	0	0
T8	7554	7427	0	0
T9	1111	971	0	0
T10	2337	2287	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	109214	0	0
T22	57216	1065	0	0
T23	5616	2696	0	0
T24	1601	34	0	0
T55	1458	0	0	0
T68	8498	0	0	0
T137	8991	0	0	0
T138	3212	0	0	0
T139	59203	495	0	0
T140	7878	0	0	0
T149	0	1885	0	0
T150	0	558	0	0
T152	0	820	0	0
T157	0	535	0	0
T158	0	583	0	0
T159	0	614	0	0
T160	15773	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	3069	0	0
T1	7142	7	0	0
T2	625	1	0	0
T3	3027	0	0	0
T4	1236	0	0	0
T5	1046	4	0	0
T6	2712	0	0	0
T7	803	1	0	0
T8	7554	0	0	0
T9	1111	1	0	0
T10	2337	0	0	0
T11	0	1	0	0
T25	0	2	0	0
T43	0	6	0	0
T46	0	2	0	0
T47	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	140	0	0
T17	19101	20	0	0
T18	0	40	0	0
T19	0	40	0	0
T28	0	20	0	0
T29	0	20	0	0
T30	305727	0	0	0
T31	1321	0	0	0
T32	1345	0	0	0
T33	22282	0	0	0
T34	5133	0	0	0
T35	58110	0	0	0
T36	66251	0	0	0
T37	8064	0	0	0
T38	1347	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	3069	0	0
T1	7142	7	0	0
T2	625	1	0	0
T3	3027	0	0	0
T4	1236	0	0	0
T5	1046	4	0	0
T6	2712	0	0	0
T7	803	1	0	0
T8	7554	0	0	0
T9	1111	1	0	0
T10	2337	0	0	0
T11	0	1	0	0
T25	0	2	0	0
T43	0	6	0	0
T46	0	2	0	0
T47	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17558838	765821	0	0
T1	7142	103	0	0
T2	625	0	0	0
T3	3027	0	0	0
T4	1236	10	0	0
T5	1046	94	0	0
T6	2712	0	0	0
T7	803	0	0	0
T8	7554	844	0	0
T9	1111	0	0	0
T10	2337	0	0	0
T15	0	11	0	0
T16	0	27	0	0
T25	0	392	0	0
T26	0	1385	0	0
T27	0	1427	0	0
T43	0	89	0	0