Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	418732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

216035

1

T1

60

T2

1

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	411603	1			T1	134		T2	1		T3	38
values[0x0]	111517	1			T1	19		T3	52		T4	28
values[0x1]	111647	1			T1	17		T3	74		T4	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	331830	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

302937

1

T1

77

T2

1

T3

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1788	1			T1	5		T3	1		T6	1
valid_sources[0x01]	2004	1			T1	6		T7	1		T10	4
valid_sources[0x02]	2405	1			T8	1		T10	11		T37	2
valid_sources[0x03]	1930	1			T6	4		T10	6		T40	4
valid_sources[0x04]	2109	1			T3	2		T7	2		T8	1
valid_sources[0x05]	2029	1			T3	3		T7	1		T10	4
valid_sources[0x06]	4736	1			T6	3		T8	1		T9	5
valid_sources[0x07]	1928	1			T6	4		T7	2		T9	6
valid_sources[0x08]	1868	1			T7	1		T8	1		T9	3
valid_sources[0x09]	1955	1			T5	1		T7	5		T10	9
valid_sources[0x0a]	2508	1			T1	7		T5	1		T6	1
valid_sources[0x0b]	1838	1			T6	4		T7	5		T10	3
valid_sources[0x0c]	1906	1			T6	2		T7	2		T9	1
valid_sources[0x0d]	1828	1			T3	2		T6	2		T10	5
valid_sources[0x0e]	1979	1			T2	1		T6	2		T7	2
valid_sources[0x0f]	2036	1			T3	1		T7	6		T8	1
valid_sources[0x10]	1889	1			T1	9		T3	2		T8	2
valid_sources[0x11]	2989	1			T3	1		T6	2		T9	2
valid_sources[0x12]	2495	1			T3	1		T7	2		T10	4
valid_sources[0x13]	1954	1			T3	4		T6	1		T10	7
valid_sources[0x14]	9000	1			T7	3		T9	2		T10	13
valid_sources[0x15]	1876	1			T3	1		T6	1		T9	2
valid_sources[0x16]	2127	1			T9	1		T10	2		T20	25
valid_sources[0x17]	1720	1			T6	1		T7	2		T10	9
valid_sources[0x18]	1863	1			T6	9		T7	4		T10	2
valid_sources[0x19]	1921	1			T3	4		T9	1		T10	1
valid_sources[0x1a]	3169	1			T6	3		T7	1		T10	6
valid_sources[0x1b]	1836	1			T10	6		T37	2		T77	1
valid_sources[0x1c]	1827	1			T8	1		T10	3		T40	2
valid_sources[0x1d]	1926	1			T1	3		T3	1		T10	10
valid_sources[0x1e]	1902	1			T3	1		T6	5		T8	1
valid_sources[0x1f]	3027	1			T9	1		T10	4		T40	4
valid_sources[0x20]	1748	1			T3	2		T6	1		T7	3
valid_sources[0x21]	1821	1			T1	7		T3	1		T10	7
valid_sources[0x22]	1813	1			T7	1		T9	1		T10	4
valid_sources[0x23]	1681	1			T8	1		T9	2		T10	5
valid_sources[0x24]	2223	1			T6	1		T7	2		T8	1
valid_sources[0x25]	1971	1			T10	6		T37	1		T20	53
valid_sources[0x26]	5117	1			T9	1		T10	7		T37	3
valid_sources[0x27]	2281	1			T1	5		T3	1		T6	3
valid_sources[0x28]	3604	1			T6	6		T7	2		T8	1
valid_sources[0x29]	2005	1			T6	1		T9	2		T10	8
valid_sources[0x2a]	18955	1			T3	3		T6	2		T7	1
valid_sources[0x2b]	1918	1			T1	7		T7	1		T10	6
valid_sources[0x2c]	2070	1			T6	4		T7	1		T10	4
valid_sources[0x2d]	1862	1			T3	1		T5	1		T7	1
valid_sources[0x2e]	2174	1			T3	1		T4	144		T6	2
valid_sources[0x2f]	4014	1			T5	1		T6	12		T8	1
valid_sources[0x30]	2266	1			T3	1		T6	2		T7	3
valid_sources[0x31]	1895	1			T6	1		T9	1		T10	8
valid_sources[0x32]	1886	1			T3	1		T5	1		T6	1
valid_sources[0x33]	1691	1			T4	15		T7	1		T9	2
valid_sources[0x34]	2356	1			T1	3		T6	4		T9	4
valid_sources[0x35]	1920	1			T7	4		T10	6		T40	1
valid_sources[0x36]	2800	1			T3	2		T6	1		T7	4
valid_sources[0x37]	3007	1			T3	2		T6	4		T7	1
valid_sources[0x38]	2031	1			T3	1		T5	1		T6	2
valid_sources[0x39]	2282	1			T3	1		T10	7		T37	3
valid_sources[0x3a]	1941	1			T6	1		T7	3		T10	4
valid_sources[0x3b]	2880	1			T9	1		T10	6		T40	1
valid_sources[0x3c]	1923	1			T3	2		T6	4		T9	4
valid_sources[0x3d]	2053	1			T3	1		T5	5		T7	1
valid_sources[0x3e]	3212	1			T7	2		T10	1		T40	2
valid_sources[0x3f]	1700	1			T3	2		T6	2		T10	5
valid_sources[0x40]	2158	1			T1	6		T5	1		T10	11
valid_sources[0x41]	1723	1			T5	1		T6	1		T10	3
valid_sources[0x42]	2691	1			T6	1		T10	7		T37	2
valid_sources[0x43]	1840	1			T6	10		T10	3		T37	3
valid_sources[0x44]	1883	1			T3	3		T6	1		T7	2
valid_sources[0x45]	2123	1			T6	4		T7	1		T9	7
valid_sources[0x46]	2901	1			T3	1		T10	8		T40	1
valid_sources[0x47]	2291	1			T10	1		T37	1		T77	1
valid_sources[0x48]	4794	1			T5	3		T6	5		T10	3
valid_sources[0x49]	1960	1			T5	3		T6	1		T7	1
valid_sources[0x4a]	2144	1			T3	3		T5	1		T6	3
valid_sources[0x4b]	8485	1			T6	2		T8	1		T9	3
valid_sources[0x4c]	2149	1			T1	4		T6	3		T10	6
valid_sources[0x4d]	1777	1			T3	1		T10	7		T40	1
valid_sources[0x4e]	1949	1			T3	1		T5	3		T6	1
valid_sources[0x4f]	2008	1			T1	2		T3	1		T6	2
valid_sources[0x50]	1830	1			T3	3		T6	1		T10	8
valid_sources[0x51]	1763	1			T1	11		T3	3		T5	2
valid_sources[0x52]	1834	1			T3	1		T4	9		T5	1
valid_sources[0x53]	1871	1			T5	4		T6	1		T7	7
valid_sources[0x54]	1793	1			T3	2		T6	3		T9	2
valid_sources[0x55]	2250	1			T7	2		T9	6		T10	5
valid_sources[0x56]	1840	1			T3	1		T6	1		T7	2
valid_sources[0x57]	1815	1			T3	1		T7	2		T10	7
valid_sources[0x58]	2012	1			T6	2		T7	1		T9	2
valid_sources[0x59]	1812	1			T10	3		T77	2		T20	43
valid_sources[0x5a]	2071	1			T5	2		T6	3		T8	1
valid_sources[0x5b]	1903	1			T3	3		T6	1		T7	2
valid_sources[0x5c]	1896	1			T3	2		T5	1		T7	3
valid_sources[0x5d]	2049	1			T3	1		T6	1		T7	2
valid_sources[0x5e]	1965	1			T3	1		T7	7		T10	10
valid_sources[0x5f]	2123	1			T3	1		T9	2		T10	5
valid_sources[0x60]	1867	1			T5	1		T8	3		T9	1
valid_sources[0x61]	2244	1			T3	2		T4	31		T6	5
valid_sources[0x62]	1882	1			T6	4		T9	10		T10	4
valid_sources[0x63]	1770	1			T6	3		T9	4		T10	7
valid_sources[0x64]	4167	1			T6	1		T7	1		T10	9
valid_sources[0x65]	1876	1			T3	1		T10	7		T40	1
valid_sources[0x66]	2019	1			T6	4		T8	2		T10	5
valid_sources[0x67]	2452	1			T3	1		T8	1		T9	1
valid_sources[0x68]	2677	1			T3	1		T5	2		T8	1
valid_sources[0x69]	2193	1			T6	2		T10	3		T40	2
valid_sources[0x6a]	1835	1			T4	16		T10	4		T20	27
valid_sources[0x6b]	1769	1			T6	3		T8	1		T10	7
valid_sources[0x6c]	2927	1			T3	1		T5	2		T6	1
valid_sources[0x6d]	2346	1			T3	2		T10	8		T40	2
valid_sources[0x6e]	2013	1			T3	2		T6	7		T7	1
valid_sources[0x6f]	2144	1			T3	1		T5	1		T6	1
valid_sources[0x70]	1837	1			T6	2		T10	7		T40	2
valid_sources[0x71]	1970	1			T6	1		T9	2		T10	6
valid_sources[0x72]	1923	1			T1	17		T5	1		T6	3
valid_sources[0x73]	2319	1			T7	1		T10	6		T40	1
valid_sources[0x74]	1915	1			T3	2		T5	2		T6	3
valid_sources[0x75]	2058	1			T6	1		T8	1		T10	7
valid_sources[0x76]	1991	1			T7	1		T10	5		T40	2
valid_sources[0x77]	1814	1			T10	5		T37	3		T20	35
valid_sources[0x78]	2117	1			T3	4		T6	1		T7	4
valid_sources[0x79]	3130	1			T6	2		T8	1		T9	1
valid_sources[0x7a]	1933	1			T1	1		T6	3		T7	1
valid_sources[0x7b]	2060	1			T5	1		T6	8		T9	2
valid_sources[0x7c]	1781	1			T6	2		T10	7		T37	3
valid_sources[0x7d]	1763	1			T1	7		T3	1		T8	1
valid_sources[0x7e]	1722	1			T6	1		T7	1		T10	3
valid_sources[0x7f]	2081	1			T3	1		T10	3		T40	1
valid_sources[0x80]	2155	1			T8	2		T10	7		T40	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

148735

1

T1

57

T2

1

T3

2

values[0x0]

all_enables

biggest_size

43188

1

T1

2

T3

22

T4

5

values[0x1]

all_enables

biggest_size

24112

1

T1

1

T3

12

T4

10