SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35050 | 1 | T74 | 298 | T75 | 413 | T145 | 394 | ||||
others[1] | 34982 | 1 | T74 | 300 | T75 | 388 | T145 | 411 | ||||
others[2] | 35102 | 1 | T24 | 1 | T74 | 323 | T75 | 398 | ||||
others[3] | 58408 | 1 | T23 | 1 | T24 | 1 | T74 | 482 | ||||
false | 13681 | 1 | T20 | 210 | T23 | 3 | T24 | 2 | ||||
true | 21618 | 1 | T1 | 1 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34917 | 1 | T25 | 1 | T74 | 307 | T75 | 396 | ||||
others[1] | 35025 | 1 | T74 | 314 | T75 | 391 | T145 | 399 | ||||
others[2] | 34715 | 1 | T24 | 1 | T25 | 2 | T74 | 292 | ||||
others[3] | 58666 | 1 | T23 | 1 | T25 | 1 | T74 | 502 | ||||
false | 9448 | 1 | T20 | 105 | T23 | 2 | T24 | 3 | ||||
true | 17446 | 1 | T1 | 1 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 543 | 1 | T4 | 7 | T7 | 3 | T8 | 1 | ||||
others[1] | 549 | 1 | T4 | 6 | T7 | 8 | T9 | 11 | ||||
others[2] | 511 | 1 | T4 | 9 | T7 | 5 | T9 | 7 | ||||
others[3] | 885 | 1 | T4 | 5 | T5 | 3 | T7 | 10 | ||||
false | 9279 | 1 | T1 | 1 | T2 | 2 | T3 | 1 | ||||
true | 2484 | 1 | T5 | 4 | T7 | 2 | T8 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |