Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T21,T53

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	17379484	4745	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	17379484	202583	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	17379484	6953231	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	17379484	202565	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	17379484	4745	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	17379484	202583	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	17379484	6953231	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	17379484	202565	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	4745	0	0
T10	23249	4	0	0
T11	15491	0	0	0
T12	573	0	0	0
T20	0	59	0	0
T21	0	77	0	0
T36	7456	0	0	0
T37	5664	0	0	0
T38	0	3	0	0
T40	5525	0	0	0
T41	533	0	0	0
T42	1654	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T53	0	39	0	0
T73	0	1	0	0
T74	0	16	0	0
T75	0	23	0	0
T76	2321	0	0	0
T77	3520	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	202583	0	0
T10	23249	48	0	0
T11	15491	0	0	0
T12	573	0	0	0
T20	0	1404	0	0
T21	0	1851	0	0
T36	7456	0	0	0
T37	5664	0	0	0
T38	0	109	0	0
T40	5525	0	0	0
T41	533	0	0	0
T42	1654	0	0	0
T43	0	12	0	0
T44	0	193	0	0
T53	0	1033	0	0
T73	0	13	0	0
T74	0	578	0	0
T75	0	1601	0	0
T76	2321	0	0	0
T77	3520	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	6953231	0	0
T1	5220	2895	0	0
T2	2532	0	0	0
T3	3244	1668	0	0
T4	4908	0	0	0
T5	7027	0	0	0
T6	6490	2643	0	0
T7	4166	0	0	0
T8	4286	0	0	0
T9	3420	0	0	0
T10	23249	10632	0	0
T13	0	75	0	0
T20	0	80028	0	0
T40	0	3080	0	0
T43	0	853	0	0
T77	0	2610	0	0
T78	0	884	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	202565	0	0
T10	23249	48	0	0
T11	15491	0	0	0
T12	573	0	0	0
T20	0	1404	0	0
T21	0	1851	0	0
T36	7456	0	0	0
T37	5664	0	0	0
T38	0	109	0	0
T40	5525	0	0	0
T41	533	0	0	0
T42	1654	0	0	0
T43	0	12	0	0
T44	0	193	0	0
T53	0	1033	0	0
T73	0	13	0	0
T74	0	578	0	0
T75	0	1601	0	0
T76	2321	0	0	0
T77	3520	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	4745	0	0
T10	23249	4	0	0
T11	15491	0	0	0
T12	573	0	0	0
T20	0	59	0	0
T21	0	77	0	0
T36	7456	0	0	0
T37	5664	0	0	0
T38	0	3	0	0
T40	5525	0	0	0
T41	533	0	0	0
T42	1654	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T53	0	39	0	0
T73	0	1	0	0
T74	0	16	0	0
T75	0	23	0	0
T76	2321	0	0	0
T77	3520	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	202583	0	0
T10	23249	48	0	0
T11	15491	0	0	0
T12	573	0	0	0
T20	0	1404	0	0
T21	0	1851	0	0
T36	7456	0	0	0
T37	5664	0	0	0
T38	0	109	0	0
T40	5525	0	0	0
T41	533	0	0	0
T42	1654	0	0	0
T43	0	12	0	0
T44	0	193	0	0
T53	0	1033	0	0
T73	0	13	0	0
T74	0	578	0	0
T75	0	1601	0	0
T76	2321	0	0	0
T77	3520	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	6953231	0	0
T1	5220	2895	0	0
T2	2532	0	0	0
T3	3244	1668	0	0
T4	4908	0	0	0
T5	7027	0	0	0
T6	6490	2643	0	0
T7	4166	0	0	0
T8	4286	0	0	0
T9	3420	0	0	0
T10	23249	10632	0	0
T13	0	75	0	0
T20	0	80028	0	0
T40	0	3080	0	0
T43	0	853	0	0
T77	0	2610	0	0
T78	0	884	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	202565	0	0
T10	23249	48	0	0
T11	15491	0	0	0
T12	573	0	0	0
T20	0	1404	0	0
T21	0	1851	0	0
T36	7456	0	0	0
T37	5664	0	0	0
T38	0	109	0	0
T40	5525	0	0	0
T41	533	0	0	0
T42	1654	0	0	0
T43	0	12	0	0
T44	0	193	0	0
T53	0	1033	0	0
T73	0	13	0	0
T74	0	578	0	0
T75	0	1601	0	0
T76	2321	0	0	0
T77	3520	0	0	0