Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17939752	15630	0	0
intr_enable_rd_A	17939752	22123	0	0
reset_en_rd_A	17939752	1797	0	0
reset_en_regwen_rd_A	17939752	1454	0	0
wake_info_capture_dis_rd_A	17939752	1410	0	0
wakeup_en_rd_A	17939752	2249	0	0
wakeup_en_regwen_rd_A	17939752	1603	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17939752	15630	0	0
T14	1402	0	0	0
T20	201694	2	0	0
T21	0	10	0	0
T22	0	4	0	0
T23	2357	0	0	0
T24	5160	0	0	0
T38	76979	0	0	0
T39	4055	0	0	0
T43	1173	0	0	0
T47	0	43	0	0
T50	0	64	0	0
T78	1168	0	0	0
T79	0	32	0	0
T80	0	176	0	0
T129	0	61	0	0
T130	0	49	0	0
T131	0	88	0	0
T132	6964	0	0	0
T133	926	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17939752	22123	0	0
T3	3244	67	0	0
T4	4908	0	0	0
T5	7027	0	0	0
T6	6490	0	0	0
T7	4166	113	0	0
T8	4286	0	0	0
T9	3420	89	0	0
T10	23249	0	0	0
T11	15491	0	0	0
T21	0	1376	0	0
T39	0	66	0	0
T40	5525	0	0	0
T43	0	3	0	0
T57	0	32	0	0
T75	0	200	0	0
T132	0	95	0	0
T134	0	17	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17939752	1797	0	0
T21	242209	1	0	0
T25	2450	0	0	0
T47	0	2	0	0
T53	73858	0	0	0
T57	7014	0	0	0
T59	0	135	0	0
T73	1264	0	0	0
T79	0	12	0	0
T82	0	8	0	0
T103	0	9	0	0
T104	0	1	0	0
T124	0	34	0	0
T135	0	5	0	0
T136	0	23	0	0
T137	1289	0	0	0
T138	1421	0	0	0
T139	2342	0	0	0
T140	1232	0	0	0
T141	1652	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17939752	1454	0	0
T21	242209	6	0	0
T25	2450	0	0	0
T47	0	23	0	0
T53	73858	0	0	0
T57	7014	0	0	0
T59	0	124	0	0
T73	1264	0	0	0
T79	0	11	0	0
T82	0	2	0	0
T103	0	4	0	0
T104	0	9	0	0
T124	0	19	0	0
T135	0	1	0	0
T136	0	5	0	0
T137	1289	0	0	0
T138	1421	0	0	0
T139	2342	0	0	0
T140	1232	0	0	0
T141	1652	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17939752	1410	0	0
T21	242209	8	0	0
T25	2450	0	0	0
T47	0	9	0	0
T53	73858	0	0	0
T57	7014	0	0	0
T59	0	102	0	0
T73	1264	0	0	0
T79	0	11	0	0
T103	0	2	0	0
T104	0	8	0	0
T124	0	4	0	0
T135	0	3	0	0
T136	0	14	0	0
T137	1289	0	0	0
T138	1421	0	0	0
T139	2342	0	0	0
T140	1232	0	0	0
T141	1652	0	0	0
T142	0	4	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17939752	2249	0	0
T21	242209	11	0	0
T25	2450	0	0	0
T47	0	6	0	0
T53	73858	0	0	0
T57	7014	0	0	0
T59	0	123	0	0
T73	1264	0	0	0
T79	0	6	0	0
T82	0	8	0	0
T103	0	1	0	0
T104	0	4	0	0
T135	0	3	0	0
T136	0	6	0	0
T137	1289	0	0	0
T138	1421	0	0	0
T139	2342	0	0	0
T140	1232	0	0	0
T141	1652	0	0	0
T142	0	7	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17939752	1603	0	0
T21	242209	7	0	0
T25	2450	0	0	0
T47	0	4	0	0
T53	73858	0	0	0
T57	7014	0	0	0
T59	0	135	0	0
T73	1264	0	0	0
T79	0	13	0	0
T82	0	4	0	0
T104	0	12	0	0
T124	0	12	0	0
T135	0	8	0	0
T136	0	19	0	0
T137	1289	0	0	0
T138	1421	0	0	0
T139	2342	0	0	0
T140	1232	0	0	0
T141	1652	0	0	0
T142	0	5	0	0