Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	17379484	39151	0	0
RomAllowCheckGoodState_A	17379484	39201	0	0
RomBlockActiveState_A	17379484	28276	0	0
RomBlockCheckGoodState_A	17379484	339386	0	0
RomIntgChkDisFalse_A	17379484	16880480	0	0
RomIntgChkDisTrue_A	17379484	131325	0	0
RstreqChkEsctimeout_A	17379484	2825	0	0
RstreqChkFsmterm_A	17379484	180	0	0
RstreqChkGlbesc_A	17379484	2828	0	0
RstreqChkMainpd_A	17379484	750547	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	39151	0	0
T1	5220	6	0	0
T2	2532	3	0	0
T3	3244	19	0	0
T4	4908	1	0	0
T5	7027	13	0	0
T6	6490	21	0	0
T7	4166	3	0	0
T8	4286	13	0	0
T9	3420	2	0	0
T10	23249	95	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	39201	0	0
T1	5220	6	0	0
T2	2532	3	0	0
T3	3244	19	0	0
T4	4908	1	0	0
T5	7027	14	0	0
T6	6490	21	0	0
T7	4166	3	0	0
T8	4286	14	0	0
T9	3420	2	0	0
T10	23249	95	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	28276	0	0
T14	1402	0	0	0
T21	242209	0	0	0
T23	2357	261	0	0
T24	5160	1135	0	0
T25	2450	258	0	0
T29	0	11	0	0
T34	0	13	0	0
T38	76979	0	0	0
T39	4055	0	0	0
T78	1168	0	0	0
T86	0	478	0	0
T92	0	221	0	0
T133	926	0	0	0
T134	0	820	0	0
T137	1289	0	0	0
T143	0	3	0	0
T144	0	136	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	339386	0	0
T14	1402	0	0	0
T20	201694	2402	0	0
T21	0	2929	0	0
T23	2357	147	0	0
T24	5160	862	0	0
T25	0	255	0	0
T38	76979	45	0	0
T39	4055	0	0	0
T43	1173	0	0	0
T53	0	1700	0	0
T74	0	2253	0	0
T75	0	4139	0	0
T78	1168	0	0	0
T132	6964	0	0	0
T133	926	0	0	0
T145	0	742	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	16880480	0	0
T1	5220	5120	0	0
T2	2532	2417	0	0
T3	3244	3169	0	0
T4	4908	4847	0	0
T5	7027	6053	0	0
T6	6490	6414	0	0
T7	4166	4092	0	0
T8	4286	3355	0	0
T9	3420	3326	0	0
T10	23249	22106	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	131325	0	0
T14	1402	0	0	0
T21	242209	0	0	0
T24	5160	479	0	0
T25	2450	1082	0	0
T38	76979	0	0	0
T39	4055	0	0	0
T57	7014	0	0	0
T74	0	819	0	0
T78	1168	0	0	0
T86	0	544	0	0
T92	0	866	0	0
T133	926	0	0	0
T134	0	756	0	0
T137	1289	0	0	0
T143	0	128	0	0
T144	0	219	0	0
T146	0	1552	0	0
T147	0	1000	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	2825	0	0
T2	2532	1	0	0
T3	3244	0	0	0
T4	4908	0	0	0
T5	7027	5	0	0
T6	6490	0	0	0
T7	4166	0	0	0
T8	4286	6	0	0
T9	3420	0	0	0
T10	23249	10	0	0
T11	15491	1	0	0
T12	0	1	0	0
T36	0	7	0	0
T37	0	8	0	0
T41	0	1	0	0
T42	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	180	0	0
T17	36984	40	0	0
T18	13993	40	0	0
T19	0	40	0	0
T26	0	40	0	0
T27	0	20	0	0
T28	21347	0	0	0
T29	24717	0	0	0
T30	772	0	0	0
T31	3177	0	0	0
T32	6156	0	0	0
T33	53661	0	0	0
T34	31828	0	0	0
T35	942	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	2828	0	0
T2	2532	1	0	0
T3	3244	0	0	0
T4	4908	0	0	0
T5	7027	5	0	0
T6	6490	0	0	0
T7	4166	0	0	0
T8	4286	6	0	0
T9	3420	0	0	0
T10	23249	10	0	0
T11	15491	1	0	0
T12	0	1	0	0
T36	0	7	0	0
T37	0	8	0	0
T41	0	1	0	0
T42	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17379484	750547	0	0
T5	7027	96	0	0
T6	6490	0	0	0
T7	4166	0	0	0
T8	4286	216	0	0
T9	3420	0	0	0
T10	23249	113	0	0
T11	15491	0	0	0
T12	573	0	0	0
T14	0	29	0	0
T20	0	5373	0	0
T23	0	247	0	0
T24	0	1582	0	0
T36	7456	221	0	0
T37	0	735	0	0
T38	0	2408	0	0
T40	5525	0	0	0