Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	458036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

226165

1

T1

124

T2

406

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	432369	1			T1	220		T2	760		T3	182
values[0x0]	125861	1			T1	68		T2	219		T3	29
values[0x1]	125971	1			T1	60		T2	233		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	362545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

321656

1

T1

159

T2

557

T3

92

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2372	1			T1	2		T2	3		T9	1
valid_sources[0x01]	2037	1			T1	5		T2	6		T39	3
valid_sources[0x02]	2106	1			T8	20		T39	3		T40	5
valid_sources[0x03]	2222	1			T2	1		T6	3		T8	12
valid_sources[0x04]	2447	1			T2	1		T39	3		T40	8
valid_sources[0x05]	2278	1			T1	1		T2	2		T39	4
valid_sources[0x06]	1979	1			T1	5		T2	7		T8	9
valid_sources[0x07]	2172	1			T1	1		T2	1		T9	1
valid_sources[0x08]	5554	1			T2	6		T39	8		T40	4
valid_sources[0x09]	2289	1			T1	1		T2	4		T3	3
valid_sources[0x0a]	2667	1			T2	2		T8	10		T39	3
valid_sources[0x0b]	2398	1			T2	1		T8	2		T9	1
valid_sources[0x0c]	2303	1			T1	2		T2	12		T8	1
valid_sources[0x0d]	2154	1			T1	4		T2	2		T8	7
valid_sources[0x0e]	2294	1			T1	3		T2	1		T6	8
valid_sources[0x0f]	2265	1			T8	17		T39	2		T40	6
valid_sources[0x10]	2489	1			T1	1		T2	3		T39	2
valid_sources[0x11]	2426	1			T2	3		T6	2		T8	11
valid_sources[0x12]	2083	1			T8	13		T39	1		T40	3
valid_sources[0x13]	3591	1			T1	1		T2	10		T3	1
valid_sources[0x14]	2187	1			T1	2		T2	9		T39	5
valid_sources[0x15]	2206	1			T2	5		T8	4		T39	1
valid_sources[0x16]	2408	1			T1	3		T2	6		T39	5
valid_sources[0x17]	2367	1			T1	2		T2	5		T39	4
valid_sources[0x18]	9444	1			T1	1		T2	4		T8	1
valid_sources[0x19]	2246	1			T2	5		T39	4		T40	7
valid_sources[0x1a]	2274	1			T2	6		T8	3		T39	3
valid_sources[0x1b]	2088	1			T1	3		T2	10		T8	10
valid_sources[0x1c]	2381	1			T2	10		T3	4		T9	2
valid_sources[0x1d]	1993	1			T1	5		T2	6		T6	3
valid_sources[0x1e]	3659	1			T2	1		T8	1		T9	1
valid_sources[0x1f]	2127	1			T2	6		T8	1		T39	2
valid_sources[0x20]	2376	1			T1	1		T2	5		T6	2
valid_sources[0x21]	2218	1			T1	1		T2	3		T6	1
valid_sources[0x22]	2234	1			T1	1		T2	2		T3	1
valid_sources[0x23]	2479	1			T1	2		T2	4		T8	3
valid_sources[0x24]	2482	1			T2	9		T3	2		T8	4
valid_sources[0x25]	2199	1			T2	5		T3	7		T6	2
valid_sources[0x26]	4512	1			T1	1		T2	9		T8	9
valid_sources[0x27]	2248	1			T2	8		T8	3		T39	1
valid_sources[0x28]	3970	1			T1	1		T2	5		T8	3
valid_sources[0x29]	2355	1			T1	5		T2	9		T6	1
valid_sources[0x2a]	3496	1			T1	1		T3	15		T8	7
valid_sources[0x2b]	2356	1			T2	3		T6	2		T8	10
valid_sources[0x2c]	2451	1			T1	2		T2	7		T9	1
valid_sources[0x2d]	10903	1			T1	3		T2	1		T8	20
valid_sources[0x2e]	2239	1			T1	2		T2	1		T40	4
valid_sources[0x2f]	2215	1			T2	1		T8	4		T39	1
valid_sources[0x30]	2583	1			T2	7		T8	1		T39	1
valid_sources[0x31]	2203	1			T1	4		T2	1		T6	2
valid_sources[0x32]	2091	1			T1	1		T2	3		T3	1
valid_sources[0x33]	2207	1			T1	1		T2	4		T8	1
valid_sources[0x34]	2215	1			T1	1		T2	6		T8	16
valid_sources[0x35]	2514	1			T1	1		T2	10		T39	2
valid_sources[0x36]	6221	1			T2	6		T3	1		T39	4
valid_sources[0x37]	2263	1			T1	1		T2	3		T3	4
valid_sources[0x38]	2050	1			T2	3		T8	13		T39	4
valid_sources[0x39]	2299	1			T1	3		T2	8		T8	2
valid_sources[0x3a]	2323	1			T2	9		T8	2		T9	3
valid_sources[0x3b]	2274	1			T2	10		T39	2		T40	7
valid_sources[0x3c]	2411	1			T2	8		T39	1		T40	4
valid_sources[0x3d]	2133	1			T9	2		T39	4		T40	4
valid_sources[0x3e]	2462	1			T1	2		T2	3		T8	2
valid_sources[0x3f]	2410	1			T1	1		T3	1		T39	4
valid_sources[0x40]	2220	1			T2	6		T8	13		T9	2
valid_sources[0x41]	2161	1			T1	2		T2	4		T6	2
valid_sources[0x42]	2353	1			T1	2		T2	4		T8	3
valid_sources[0x43]	2142	1			T2	11		T6	2		T8	2
valid_sources[0x44]	2430	1			T2	3		T8	5		T39	2
valid_sources[0x45]	2127	1			T1	3		T2	1		T6	1
valid_sources[0x46]	2209	1			T2	8		T3	6		T9	3
valid_sources[0x47]	2198	1			T1	1		T2	2		T39	4
valid_sources[0x48]	2079	1			T2	6		T9	1		T39	3
valid_sources[0x49]	2157	1			T1	4		T2	2		T8	26
valid_sources[0x4a]	2101	1			T2	6		T39	1		T40	6
valid_sources[0x4b]	2188	1			T8	8		T9	2		T39	2
valid_sources[0x4c]	2420	1			T2	4		T3	11		T8	2
valid_sources[0x4d]	2183	1			T1	4		T2	2		T8	1
valid_sources[0x4e]	2393	1			T1	3		T2	9		T9	2
valid_sources[0x4f]	2263	1			T2	3		T6	1		T39	2
valid_sources[0x50]	3839	1			T1	2		T2	6		T3	1
valid_sources[0x51]	2244	1			T1	1		T2	8		T3	12
valid_sources[0x52]	3056	1			T1	2		T2	1		T6	2
valid_sources[0x53]	3823	1			T1	7		T2	4		T8	5
valid_sources[0x54]	2651	1			T1	3		T2	6		T39	1
valid_sources[0x55]	3046	1			T1	1		T2	6		T9	2
valid_sources[0x56]	2180	1			T1	3		T2	4		T39	5
valid_sources[0x57]	2128	1			T2	3		T8	2		T39	7
valid_sources[0x58]	2449	1			T1	2		T2	3		T9	3
valid_sources[0x59]	2465	1			T1	1		T2	8		T3	3
valid_sources[0x5a]	2727	1			T1	3		T2	7		T8	16
valid_sources[0x5b]	2329	1			T2	1		T8	13		T9	4
valid_sources[0x5c]	2348	1			T2	1		T8	10		T39	4
valid_sources[0x5d]	2003	1			T1	1		T2	3		T8	9
valid_sources[0x5e]	2153	1			T6	2		T8	7		T9	2
valid_sources[0x5f]	2226	1			T2	9		T8	7		T39	2
valid_sources[0x60]	2327	1			T1	2		T2	4		T3	2
valid_sources[0x61]	2706	1			T2	3		T39	5		T40	4
valid_sources[0x62]	2274	1			T2	8		T8	1		T9	2
valid_sources[0x63]	2253	1			T2	2		T8	5		T9	1
valid_sources[0x64]	2445	1			T1	1		T2	2		T39	1
valid_sources[0x65]	2152	1			T8	5		T39	5		T40	4
valid_sources[0x66]	2155	1			T2	2		T8	16		T39	1
valid_sources[0x67]	2378	1			T2	3		T39	4		T40	7
valid_sources[0x68]	1952	1			T2	9		T8	5		T9	1
valid_sources[0x69]	2104	1			T1	2		T2	4		T6	3
valid_sources[0x6a]	2684	1			T1	2		T2	3		T8	1
valid_sources[0x6b]	3199	1			T2	2		T3	4		T8	4
valid_sources[0x6c]	3878	1			T2	2		T39	4		T40	2
valid_sources[0x6d]	2062	1			T1	4		T2	2		T8	10
valid_sources[0x6e]	2229	1			T2	3		T6	1		T8	4
valid_sources[0x6f]	2144	1			T2	4		T3	2		T6	1
valid_sources[0x70]	2409	1			T1	2		T2	5		T3	3
valid_sources[0x71]	2501	1			T2	4		T6	2		T9	4
valid_sources[0x72]	2152	1			T1	2		T2	7		T8	3
valid_sources[0x73]	2311	1			T1	3		T2	10		T3	1
valid_sources[0x74]	2228	1			T1	1		T2	7		T8	1
valid_sources[0x75]	2258	1			T2	5		T8	10		T9	1
valid_sources[0x76]	3400	1			T1	1		T2	4		T39	4
valid_sources[0x77]	2249	1			T2	2		T3	4		T39	3
valid_sources[0x78]	2150	1			T1	1		T2	4		T9	2
valid_sources[0x79]	2283	1			T2	4		T8	14		T39	5
valid_sources[0x7a]	2306	1			T1	2		T2	7		T8	22
valid_sources[0x7b]	2678	1			T1	3		T2	1		T8	5
valid_sources[0x7c]	2244	1			T2	4		T8	6		T39	2
valid_sources[0x7d]	2271	1			T2	7		T8	17		T39	1
valid_sources[0x7e]	3304	1			T1	1		T2	11		T3	3
valid_sources[0x7f]	7349	1			T1	1		T2	2		T3	4
valid_sources[0x80]	4229	1			T1	1		T2	9		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

151839

1

T1

86

T2

289

T3

17

values[0x0]

all_enables

biggest_size

47863

1

T1

24

T2

77

T3

7

values[0x1]

all_enables

biggest_size

26463

1

T1

14

T2

40

T3

7