SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35074 | 1 | T2 | 299 | T5 | 402 | T8 | 383 | ||||
others[1] | 35208 | 1 | T2 | 303 | T5 | 398 | T8 | 418 | ||||
others[2] | 34779 | 1 | T2 | 302 | T5 | 405 | T8 | 398 | ||||
others[3] | 58540 | 1 | T2 | 500 | T5 | 666 | T8 | 665 | ||||
false | 14735 | 1 | T2 | 50 | T5 | 50 | T8 | 50 | ||||
true | 23090 | 1 | T1 | 1 | T2 | 51 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35206 | 1 | T2 | 290 | T5 | 415 | T8 | 417 | ||||
others[1] | 35041 | 1 | T2 | 293 | T5 | 401 | T8 | 400 | ||||
others[2] | 35220 | 1 | T2 | 306 | T5 | 395 | T8 | 403 | ||||
others[3] | 58049 | 1 | T2 | 527 | T5 | 672 | T8 | 661 | ||||
false | 9960 | 1 | T2 | 50 | T5 | 50 | T8 | 50 | ||||
true | 18373 | 1 | T1 | 1 | T2 | 51 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 565 | 1 | T3 | 7 | T14 | 1 | T161 | 7 | ||||
others[1] | 528 | 1 | T3 | 9 | T13 | 1 | T27 | 1 | ||||
others[2] | 550 | 1 | T3 | 2 | T9 | 1 | T13 | 1 | ||||
others[3] | 939 | 1 | T3 | 9 | T9 | 1 | T27 | 1 | ||||
false | 10104 | 1 | T1 | 1 | T2 | 1 | T3 | 3 | ||||
true | 2787 | 1 | T9 | 8 | T13 | 6 | T14 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |