Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18579055	16192	0	0
intr_enable_rd_A	18579055	17609	0	0
reset_en_rd_A	18579055	1633	0	0
reset_en_regwen_rd_A	18579055	1440	0	0
wake_info_capture_dis_rd_A	18579055	1515	0	0
wakeup_en_rd_A	18579055	2794	0	0
wakeup_en_regwen_rd_A	18579055	1346	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18579055	16192	0	0
T23	114093	1	0	0
T24	0	2	0	0
T25	0	85	0	0
T54	0	97	0	0
T55	0	6	0	0
T73	0	9	0	0
T126	0	2	0	0
T127	0	10	0	0
T128	0	1	0	0
T129	0	3	0	0
T130	2289	0	0	0
T131	1166	0	0	0
T132	15893	0	0	0
T133	2181	0	0	0
T134	12135	0	0	0
T135	2598	0	0	0
T136	4982	0	0	0
T137	7170	0	0	0
T138	2324	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18579055	17609	0	0
T3	3443	58	0	0
T4	3006	0	0	0
T5	26513	160	0	0
T6	2278	41	0	0
T7	666	0	0	0
T8	20025	0	0	0
T9	4037	17	0	0
T10	10316	29	0	0
T11	783	0	0	0
T26	0	221	0	0
T39	20898	0	0	0
T60	0	20	0	0
T61	0	67	0	0
T139	0	10	0	0
T140	0	72	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18579055	1633	0	0
T20	37155	0	0	0
T30	968	0	0	0
T31	106006	0	0	0
T32	6394	0	0	0
T33	828	0	0	0
T34	5538	0	0	0
T35	2931	0	0	0
T53	0	114	0	0
T58	0	25	0	0
T59	0	14	0	0
T62	0	3	0	0
T65	0	14	0	0
T77	0	67	0	0
T108	0	16	0	0
T110	0	37	0	0
T124	0	43	0	0
T126	90655	2	0	0
T127	170633	0	0	0
T141	5222	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18579055	1440	0	0
T20	37155	0	0	0
T30	968	0	0	0
T31	106006	0	0	0
T32	6394	0	0	0
T33	828	0	0	0
T34	5538	0	0	0
T35	2931	0	0	0
T53	0	104	0	0
T58	0	38	0	0
T59	0	14	0	0
T62	0	2	0	0
T65	0	31	0	0
T77	0	35	0	0
T108	0	3	0	0
T110	0	76	0	0
T126	90655	1	0	0
T127	170633	0	0	0
T141	5222	0	0	0
T142	0	8	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18579055	1515	0	0
T20	37155	0	0	0
T30	968	0	0	0
T31	106006	0	0	0
T32	6394	0	0	0
T33	828	0	0	0
T34	5538	0	0	0
T35	2931	0	0	0
T53	0	107	0	0
T58	0	13	0	0
T59	0	28	0	0
T62	0	34	0	0
T65	0	35	0	0
T77	0	40	0	0
T108	0	9	0	0
T110	0	55	0	0
T124	0	12	0	0
T126	90655	2	0	0
T127	170633	0	0	0
T141	5222	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18579055	2794	0	0
T20	37155	0	0	0
T30	968	0	0	0
T31	106006	0	0	0
T32	6394	0	0	0
T33	828	0	0	0
T34	5538	0	0	0
T35	2931	0	0	0
T53	0	319	0	0
T58	0	26	0	0
T59	0	11	0	0
T62	0	1	0	0
T65	0	15	0	0
T77	0	149	0	0
T108	0	29	0	0
T110	0	30	0	0
T124	0	33	0	0
T126	90655	1	0	0
T127	170633	0	0	0
T141	5222	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18579055	1346	0	0
T20	37155	0	0	0
T30	968	0	0	0
T31	106006	0	0	0
T32	6394	0	0	0
T33	828	0	0	0
T34	5538	0	0	0
T35	2931	0	0	0
T53	0	90	0	0
T58	0	5	0	0
T59	0	17	0	0
T62	0	19	0	0
T65	0	17	0	0
T77	0	21	0	0
T110	0	69	0	0
T124	0	23	0	0
T126	90655	2	0	0
T127	170633	0	0	0
T141	5222	0	0	0
T143	0	131	0	0