Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	17971227	39931	0	0
IoStatusRise_A	17971227	44370	0	0
MainStatusFall_A	17971227	39931	0	0
MainStatusRise_A	17971227	44371	0	0
UsbStatusFall_A	17971227	30510	0	0
UsbStatusRise_A	17971227	34199	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	39931	0	0
T1	5155	17	0	0
T2	55838	88	0	0
T3	3443	0	0	0
T4	3006	4	0	0
T5	26513	87	0	0
T6	2278	11	0	0
T7	666	1	0	0
T8	20025	85	0	0
T9	4037	14	0	0
T10	10316	16	0	0
T11	0	1	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	44370	0	0
T1	5155	18	0	0
T2	55838	89	0	0
T3	3443	1	0	0
T4	3006	5	0	0
T5	26513	89	0	0
T6	2278	12	0	0
T7	666	3	0	0
T8	20025	87	0	0
T9	4037	16	0	0
T10	10316	17	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	39931	0	0
T1	5155	17	0	0
T2	55838	88	0	0
T3	3443	0	0	0
T4	3006	4	0	0
T5	26513	87	0	0
T6	2278	11	0	0
T7	666	1	0	0
T8	20025	85	0	0
T9	4037	14	0	0
T10	10316	16	0	0
T11	0	1	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	44371	0	0
T1	5155	18	0	0
T2	55838	89	0	0
T3	3443	1	0	0
T4	3006	5	0	0
T5	26513	89	0	0
T6	2278	12	0	0
T7	666	3	0	0
T8	20025	87	0	0
T9	4037	16	0	0
T10	10316	17	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	30510	0	0
T1	5155	14	0	0
T2	55838	48	0	0
T3	3443	0	0	0
T4	3006	4	0	0
T5	26513	43	0	0
T6	2278	11	0	0
T7	666	1	0	0
T8	20025	52	0	0
T9	4037	14	0	0
T10	10316	11	0	0
T11	0	1	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	34199	0	0
T1	5155	15	0	0
T2	55838	48	0	0
T3	3443	1	0	0
T4	3006	5	0	0
T5	26513	45	0	0
T6	2278	12	0	0
T7	666	3	0	0
T8	20025	53	0	0
T9	4037	16	0	0
T10	10316	11	0	0