Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	17971227	43983	0	0
RomAllowCheckGoodState_A	17971227	44033	0	0
RomBlockActiveState_A	17971227	26497	0	0
RomBlockCheckGoodState_A	17971227	393789	0	0
RomIntgChkDisFalse_A	17971227	17398090	0	0
RomIntgChkDisTrue_A	17971227	173595	0	0
RstreqChkEsctimeout_A	17971227	3094	0	0
RstreqChkFsmterm_A	17971227	140	0	0
RstreqChkGlbesc_A	17971227	3094	0	0
RstreqChkMainpd_A	17971227	746271	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	43983	0	0
T1	5155	18	0	0
T2	55838	89	0	0
T3	3443	1	0	0
T4	3006	5	0	0
T5	26513	89	0	0
T6	2278	12	0	0
T7	666	3	0	0
T8	20025	87	0	0
T9	4037	16	0	0
T10	10316	17	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	44033	0	0
T1	5155	18	0	0
T2	55838	89	0	0
T3	3443	1	0	0
T4	3006	5	0	0
T5	26513	89	0	0
T6	2278	12	0	0
T7	666	3	0	0
T8	20025	87	0	0
T9	4037	16	0	0
T10	10316	17	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	26497	0	0
T5	26513	7	0	0
T6	2278	0	0	0
T7	666	0	0	0
T8	20025	0	0	0
T9	4037	0	0	0
T10	10316	0	0	0
T11	783	0	0	0
T13	2829	0	0	0
T14	0	1056	0	0
T27	0	593	0	0
T39	20898	0	0	0
T40	59382	0	0	0
T80	0	8	0	0
T145	0	933	0	0
T146	0	13	0	0
T147	0	7	0	0
T148	0	235	0	0
T149	0	4	0	0
T150	0	192	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	393789	0	0
T2	55838	4025	0	0
T3	3443	0	0	0
T4	3006	0	0	0
T5	26513	1310	0	0
T6	2278	0	0	0
T7	666	0	0	0
T8	20025	1332	0	0
T9	4037	0	0	0
T10	10316	0	0	0
T11	783	0	0	0
T14	0	836	0	0
T26	0	850	0	0
T27	0	252	0	0
T39	0	459	0	0
T40	0	3876	0	0
T79	0	413	0	0
T80	0	1316	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	17398090	0	0
T1	5155	5101	0	0
T2	55838	54774	0	0
T3	3443	3377	0	0
T4	3006	2672	0	0
T5	26513	26370	0	0
T6	2278	2196	0	0
T7	666	495	0	0
T8	20025	19846	0	0
T9	4037	3853	0	0
T10	10316	10253	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	173595	0	0
T2	55838	981	0	0
T3	3443	0	0	0
T4	3006	0	0	0
T5	26513	0	0	0
T6	2278	0	0	0
T7	666	0	0	0
T8	20025	0	0	0
T9	4037	0	0	0
T10	10316	0	0	0
T11	783	0	0	0
T14	0	2374	0	0
T27	0	346	0	0
T145	0	2591	0	0
T147	0	299	0	0
T148	0	74	0	0
T149	0	199	0	0
T151	0	1315	0	0
T152	0	2049	0	0
T153	0	906	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	3094	0	0
T7	666	1	0	0
T8	20025	0	0	0
T9	4037	7	0	0
T10	10316	0	0	0
T11	783	1	0	0
T12	0	1	0	0
T13	2829	5	0	0
T14	5812	3	0	0
T27	0	4	0	0
T39	20898	0	0	0
T40	59382	0	0	0
T41	0	3	0	0
T42	0	6	0	0
T44	5202	0	0	0
T45	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	140	0	0
T20	37155	40	0	0
T21	0	20	0	0
T22	0	20	0	0
T28	0	20	0	0
T29	0	40	0	0
T30	968	0	0	0
T31	106006	0	0	0
T32	6394	0	0	0
T33	828	0	0	0
T34	5538	0	0	0
T35	2931	0	0	0
T36	52463	0	0	0
T37	62048	0	0	0
T38	49655	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	3094	0	0
T7	666	1	0	0
T8	20025	0	0	0
T9	4037	7	0	0
T10	10316	0	0	0
T11	783	1	0	0
T12	0	1	0	0
T13	2829	5	0	0
T14	5812	3	0	0
T27	0	4	0	0
T39	20898	0	0	0
T40	59382	0	0	0
T41	0	3	0	0
T42	0	6	0	0
T44	5202	0	0	0
T45	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17971227	746271	0	0
T2	55838	5666	0	0
T3	3443	0	0	0
T4	3006	0	0	0
T5	26513	1892	0	0
T6	2278	0	0	0
T7	666	0	0	0
T8	20025	1851	0	0
T9	4037	281	0	0
T10	10316	0	0	0
T11	783	0	0	0
T13	0	102	0	0
T14	0	2008	0	0
T27	0	405	0	0
T39	0	1300	0	0
T40	0	6703	0	0
T41	0	137	0	0